test: update and add auto-check

test/test_analyzer.py

@@ -1,4 +1,4 @@
-# This file is Copyright (c) 2017-2018 Florent Kermarrec <florent@enjoy-digital.fr>
+# This file is Copyright (c) 2017-2019 Florent Kermarrec <florent@enjoy-digital.fr>
 # License: BSD
 
 import unittest
@@ -7,45 +7,42 @@ from migen import *
 
 from litescope import LiteScopeAnalyzer
 
-#TODO:
-# - improve testing with a software model and check that the implementation
-#   has a similar behaviour.
-
-
-class DUT(Module):
-    def __init__(self):
-        counter = Signal(16)
-        self.sync += counter.eq(counter + 1)
-
-        self.submodules.analyzer = LiteScopeAnalyzer(counter, 512)
-
-
-def main_generator(dut):
-    yield from dut.analyzer.frontend.trigger.value.write(0x0080)
-    yield from dut.analyzer.frontend.trigger.mask.write(0xfff0)
-    yield from dut.analyzer.frontend.subsampler.value.write(2)
-    yield
-    yield from dut.analyzer.storage.length.write(256)
-    yield from dut.analyzer.storage.offset.write(8)
-    for i in range(16):
-        yield
-    yield from dut.analyzer.storage.start.write(1)
-    yield
-    while not (yield from dut.analyzer.storage.idle.read()):
-        yield
-    data = []
-    while (yield from dut.analyzer.storage.mem_valid.read()):
-        data.append((yield from dut.analyzer.storage.mem_data.read()))
-        yield from dut.analyzer.storage.mem_ready.write(1)
-        yield
-
-    print(data)
-    print(len(data))
-
 
 class TestAnalyzer(unittest.TestCase):
-    def test(self):
+    def test_analyzer(self):
+        def generator(dut):
+            dut.data = []
+            # Configure Trigger
+            yield from dut.analyzer.trigger.mem_value.write(0x0010)
+            yield from dut.analyzer.trigger.mem_mask.write(0xffff)
+            yield from dut.analyzer.trigger.mem_write.write(1)
+
+            # Configure Subsampler
+            yield from dut.analyzer.subsampler.value.write(2)
+
+            # Configure Storage
+            yield from dut.analyzer.storage.length.write(256)
+            yield from dut.analyzer.storage.offset.write(8)
+            yield from dut.analyzer.storage.enable.write(1)
+            yield
+            for i in range(16):
+                yield
+            # Wait capture
+            while not (yield from dut.analyzer.storage.done.read()):
+                yield
+            # Reade captured datas
+            while (yield from dut.analyzer.storage.mem_valid.read()):
+                dut.data.append((yield from dut.analyzer.storage.mem_data.read()))
+                yield
+
+        class DUT(Module):
+            def __init__(self):
+                counter = Signal(16)
+                self.sync += counter.eq(counter + 1)
+                self.submodules.analyzer = LiteScopeAnalyzer(counter, 512)
+
         dut = DUT()
-        generators = {"sys" : [main_generator(dut)]}
+        generators = {"sys" : [generator(dut)]}
-        clocks = {"sys": 10}
+        clocks     = {"sys": 10, "scope": 10}
-        run_simulation(dut, generators, clocks, vcd_name="sim.vcd")
+        run_simulation(dut, generators, clocks)
+        self.assertEqual(dut.data, [524 + 3*i for i in range(256)])

test/test_dump.py

@@ -8,7 +8,7 @@ from math import cos, sin
 from litescope.software.dump import *
 
 #TODO:
-# - find a way to check if files are generated corectly
+# - find a way to check if files are generated correctly
 
 dump = Dump()
 for i in range(4):