From 65b7f08cbc37d7b6de615064402d5ec3db3de3a1 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 28 May 2018 19:41:44 +0200 Subject: [PATCH] core: add full flag for trigger memory --- litescope/core.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/litescope/core.py b/litescope/core.py index 1222db8..1a0bb94 100644 --- a/litescope/core.py +++ b/litescope/core.py @@ -38,6 +38,7 @@ class FrontendTrigger(Module, AutoCSR): self.mem_write = CSR() self.mem_mask = CSRStorage(dw) self.mem_value = CSRStorage(dw) + self.mem_full = CSRStatus() # # # @@ -58,7 +59,8 @@ class FrontendTrigger(Module, AutoCSR): self.comb += [ mem.sink.valid.eq(self.mem_write.re), mem.sink.mask.eq(self.mem_mask.storage), - mem.sink.value.eq(self.mem_value.storage) + mem.sink.value.eq(self.mem_value.storage), + self.mem_full.status.eq(~mem.sink.ready) ] # hit and memory read/flush