diff --git a/README b/README
index 06fc7fd..d1040da 100644
--- a/README
+++ b/README
@@ -19,9 +19,9 @@ LiteScope is a small footprint and configurable embedded logic analyzer that you
 can use in your FPGA and aims to provide a free, portable and flexible
 alternative to vendor's solutions!
 
-LiteScope is part of EnjoyDigital's libraries whose aims are to lower entry level of
+LiteScope is part of LiteX libraries whose aims are to lower entry level of
 complex FPGA cores by providing simple, elegant and efficient implementations
-ofcomponents used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
+of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
 
 The core uses simple and specific streaming buses and will provides in the future
 adapters to use standardized AXI or Avalon-ST streaming buses.
@@ -29,11 +29,12 @@ adapters to use standardized AXI or Avalon-ST streaming buses.
 Since Python is used to describe the HDL, the core is highly and easily
 configurable.
 
-LiteScope uses technologies developed in partnership with M-Labs Ltd:
+LiteScope is built using LiteX and uses technologies developed in partnership with
+M-Labs Ltd:
  - Migen enables generating HDL with Python in an efficient way.
  - MiSoC provides the basic blocks to build a powerful and small footprint SoC.
 
-LiteScope can be used as MiSoC library or can be integrated with your standard
+LiteScope can be used as LiteX library or can be integrated with your standard
 design flow by generating the verilog rtl that you will use as a standard core.
 
 [> Features
@@ -73,22 +74,19 @@ devel [AT] lists.m-labs.hk.
 -------------------
 1. Install Python3 and your vendor's software
 
-2. Obtain Migen and install it:
-  git clone https://github.com/enjoy-digital/migen
-  cd migen
+2. Obtain LiteX and install it:
+  git clone https://github.com/enjoy-digital/litex --recursive
+  cd litex
   python3 setup.py install
   cd ..
 
-3. Obtain MiSoC:
-  git clone https://github.com/enjoy-digital/misoc --recursive
-
-4. Build and load test design:
+3. Build and load test design:
   go to example_designs/
   ./make.py -p [your_platform] all load-bitstream
   Supported platforms are the ones already supported by Mibuild:
   de0nano, m1, mixxeo, kc705, zedboard...
 
-5. Test design:
+4. Test design:
   go to test and run:
   ./make.py --port your_serial_port test_inout (will blink leds)
   ./make.py --port your_serial_port test_logic_analyzer (will capture counter)