diff --git a/README b/README
index 57c07e0..1cc5a1f 100644
--- a/README
+++ b/README
@@ -94,12 +94,11 @@ devel [AT] lists.m-labs.hk.
 
 6. Test design:
   go to test and run:
-  ./make.py --port your_serial_port test_io (will blink leds)
-  ./make.py --port your_serial_port test_la (will capture counter)
+  ./make.py --port your_serial_port test_inout (will blink leds)
+  ./make.py --port your_serial_port test_logic_analyzer (will capture counter)
 
   tests can also be executed over Etherbone (provided with LiteEth):
-  ./make.py --ip_address fpga_ip_address test_io
-  ./make.py --ip_address fpga_ip_address test_la
+  ./make.py --ip_address fpga_ip_address your_test
 
 [> Simulations:
   XXX convert simulations
diff --git a/example_designs/make.py b/example_designs/make.py
index 6fe8ef4..bbda05a 100644
--- a/example_designs/make.py
+++ b/example_designs/make.py
@@ -116,15 +116,15 @@ if __name__ == "__main__":
        logic analyzer core powered by Migen
 
 ====== Building parameters: ======""")
-if hasattr(soc, "io"):
+if hasattr(soc, "inout"):
     print("""
 LiscopeIO
 ---------
 Width: {}
-""".format(soc.io.dw)
+""".format(soc.inout.dw)
 )
 
-if hasattr(soc, "la"):
+if hasattr(soc, "logic_analyzer"):
     print("""
 LiscopeLA
 ---------
@@ -133,10 +133,10 @@ Depth: {}
 Subsampler: {}
 RLE: {}
 ===============================""".format(
-    soc.la.dw,
-    soc.la.depth,
-    str(soc.la.with_subsampler),
-    str(soc.la.with_rle)
+    soc.logic_analyzer.dw,
+    soc.logic_analyzer.depth,
+    str(soc.logic_analyzer.with_subsampler),
+    str(soc.logic_analyzer.with_rle)
     )
 )
 
diff --git a/example_designs/targets/core.py b/example_designs/targets/core.py
index d35a2dc..78dd654 100644
--- a/example_designs/targets/core.py
+++ b/example_designs/targets/core.py
@@ -1,3 +1,4 @@
+from migen.fhdl.std import *
 from migen.genlib.io import CRG
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
@@ -7,10 +8,10 @@ from mibuild.xilinx.platform import XilinxPlatform
 from targets import *
 
 from misoclib.soc import SoC
-from litescope.common import *
+
 from litescope.core.port import LiteScopeTerm
-from litescope.frontend.io import LiteScopeIO
-from litescope.frontend.la import LiteScopeLA
+from litescope.frontend.inout import LiteScopeInOut
+from litescope.frontend.logic_analyzer import LiteScopeLogicAnalyzer
 
 
 _io = [
@@ -38,7 +39,7 @@ class CorePlatform(XilinxPlatform):
 class Core(SoC):
     platform = CorePlatform()
     csr_map = {
-        "la":    16
+        "logic_analyzer":    16
     }
     csr_map.update(SoC.csr_map)
 
@@ -56,8 +57,8 @@ class Core(SoC):
         self.add_wb_master(self.cpu_or_bridge.wishbone)
 
         self.bus = platform.request("bus")
-        self.submodules.la = LiteScopeLA((self.bus), 512, with_rle=True, with_subsampler=True)
-        self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
+        self.submodules.logic_analyzer = LiteScopeLogicAnalyzer((self.bus), 512, with_rle=True, with_subsampler=True)
+        self.logic_analyzer.trigger.add_port(LiteScopeTerm(self.logic_analyzer.dw))
 
     def get_ios(self):
         ios = set()
diff --git a/example_designs/targets/simple.py b/example_designs/targets/simple.py
index 39c9caa..adc1b3e 100644
--- a/example_designs/targets/simple.py
+++ b/example_designs/targets/simple.py
@@ -1,17 +1,18 @@
 from migen.genlib.io import CRG
 
 from misoclib.soc import SoC
+
 from litescope.common import *
 from litescope.core.port import LiteScopeTerm
-from litescope.frontend.io import LiteScopeIO
-from litescope.frontend.la import LiteScopeLA
+from litescope.frontend.inout import LiteScopeInOut
+from litescope.frontend.logic_analyzer import LiteScopeLogicAnalyzer
 
 from misoclib.com.uart.bridge import UARTWishboneBridge
 
 class LiteScopeSoC(SoC):
     csr_map = {
-        "io":    16,
-        "la":    17
+        "inout" :          16,
+        "logic_analyzer" : 17
     }
     csr_map.update(SoC.csr_map)
 
@@ -28,10 +29,10 @@ class LiteScopeSoC(SoC):
         self.add_wb_master(self.cpu_or_bridge.wishbone)
         self.submodules.crg = CRG(platform.request(platform.default_clk_name))
 
-        self.submodules.io = LiteScopeIO(8)
+        self.submodules.inout = LiteScopeInOut(8)
         for i in range(8):
             try:
-                self.comb += platform.request("user_led", i).eq(self.io.o[i])
+                self.comb += platform.request("user_led", i).eq(self.inout.o[i])
             except:
                 pass
 
@@ -48,10 +49,10 @@ class LiteScopeSoC(SoC):
         self.debug = (
             counter1.value
         )
-        self.submodules.la = LiteScopeLA(self.debug, 512, with_rle=True, with_subsampler=True)
-        self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
+        self.submodules.logic_analyzer = LiteScopeLogicAnalyzer(self.debug, 512, with_rle=True, with_subsampler=True)
+        self.logic_analyzer.trigger.add_port(LiteScopeTerm(self.logic_analyzer.dw))
 
     def do_exit(self, vns):
-        self.la.export(vns, "test/la.csv")
+        self.logic_analyzer.export(vns, "test/logic_analyzer.csv")
 
 default_subtarget = LiteScopeSoC
diff --git a/example_designs/test/Makefile b/example_designs/test/Makefile
index 7c8e8a7..46e865b 100644
--- a/example_designs/test/Makefile
+++ b/example_designs/test/Makefile
@@ -4,10 +4,13 @@ SERIAL ?= 2
 
 CMD = PYTHONPATH=$(COREDIR) $(PYTHON) make.py --port $(SERIAL)
 
-test_io:
-	$(CMD) test_io
+test_regs:
+	$(CMD) test_regs
 
-test_la:
-	$(CMD) test_la
+test_inout:
+	$(CMD) test_inout
 
-all: test_io test_la
+test_logic_analyzer:
+	$(CMD) test_logic_analyzer
+
+all: test_regs test_inout test_logic_analyzer
\ No newline at end of file
diff --git a/example_designs/test/test_io.py b/example_designs/test/test_inout.py
similarity index 55%
rename from example_designs/test/test_io.py
rename to example_designs/test/test_inout.py
index c3b0ae7..115e7ba 100644
--- a/example_designs/test/test_io.py
+++ b/example_designs/test/test_inout.py
@@ -1,37 +1,37 @@
 import time
-from litescope.software.driver.io import LiteScopeIODriver
+from litescope.software.driver.inout import LiteScopeInOutDriver
 
 
-def led_anim0(io):
+def led_anim0(inout):
     for i in range(10):
-        io.write(0xA5)
+        inout.write(0xA5)
         time.sleep(0.1)
-        io.write(0x5A)
+        inout.write(0x5A)
         time.sleep(0.1)
 
 
-def led_anim1(io):
+def led_anim1(inout):
     for j in range(4):
         # Led <<
         led_data = 1
         for i in range(8):
-            io.write(led_data)
+            inout.write(led_data)
             time.sleep(i*i*0.0020)
             led_data = (led_data << 1)
         # Led >>
         ledData = 128
         for i in range(8):
-            io.write(led_data)
+            inout.write(led_data)
             time.sleep(i*i*0.0020)
             led_data = (led_data >> 1)
 
 
 def main(wb):
-    io = LiteScopeIODriver(wb.regs, "io")
+    inout = LiteScopeInOutDriver(wb.regs, "inout")
     wb.open()
     # # #
-    led_anim0(io)
-    led_anim1(io)
-    print("{:02X}".format(io.read()))
+    led_anim0(inout)
+    led_anim1(inout)
+    print("{:02X}".format(inout.read()))
     # # #
     wb.close()
diff --git a/example_designs/test/test_la.py b/example_designs/test/test_logic_analyzer.py
similarity index 66%
rename from example_designs/test/test_la.py
rename to example_designs/test/test_logic_analyzer.py
index f926ae3..722a684 100644
--- a/example_designs/test/test_la.py
+++ b/example_designs/test/test_logic_analyzer.py
@@ -1,13 +1,12 @@
-from litescope.software.driver.la import LiteScopeLADriver
+from litescope.software.driver.logic_analyzer import LiteScopeLogicAnalyzerDriver
 
 
 def main(wb):
     wb.open()
     # # #
-    la = LiteScopeLADriver(wb.regs, "la", debug=True)
+    la = LiteScopeLogicAnalyzerDriver(wb.regs, "logic_analyzer", debug=True)
 
-    # cond = {"cnt0"    :    128} # trigger on cnt0 = 128
-    cond = {}  # trigger on cnt0 = 128
+    cond = {} # immediate trigger
     la.configure_term(port=0, cond=cond)
     la.configure_sum("term")
     la.configure_subsampler(1)
diff --git a/litescope/frontend/io.py b/litescope/frontend/inout.py
similarity index 85%
rename from litescope/frontend/io.py
rename to litescope/frontend/inout.py
index 96b62ba..6fb9c99 100644
--- a/litescope/frontend/io.py
+++ b/litescope/frontend/inout.py
@@ -1,7 +1,7 @@
 from litescope.common import *
 
 
-class LiteScopeIO(Module, AutoCSR):
+class LiteScopeInOut(Module, AutoCSR):
     def __init__(self, dw):
         self.dw = dw
         self._input = CSRStatus(dw)
diff --git a/litescope/frontend/la.py b/litescope/frontend/logic_analyzer.py
similarity index 98%
rename from litescope/frontend/la.py
rename to litescope/frontend/logic_analyzer.py
index 5ee602c..05dee12 100644
--- a/litescope/frontend/la.py
+++ b/litescope/frontend/logic_analyzer.py
@@ -5,7 +5,7 @@ from litescope.core.storage import LiteScopeSubSampler, LiteScopeRecorder, LiteS
 from mibuild.tools import write_to_file
 
 
-class LiteScopeLA(Module, AutoCSR):
+class LiteScopeLogicAnalyzer(Module, AutoCSR):
     def __init__(self, layout, depth, clk_domain="sys",
             with_input_buffer=False,
             with_rle=False, rle_length=256,
diff --git a/litescope/software/driver/io.py b/litescope/software/driver/inout.py
similarity index 93%
rename from litescope/software/driver/io.py
rename to litescope/software/driver/inout.py
index a8019d7..d46f317 100644
--- a/litescope/software/driver/io.py
+++ b/litescope/software/driver/inout.py
@@ -1,4 +1,4 @@
-class LiteScopeIODriver():
+class LiteScopeInOutDriver():
     def __init__(self, regs, name):
         self.regs = regs
         self.name = name
diff --git a/litescope/software/driver/la.py b/litescope/software/driver/logic_analyzer.py
similarity index 99%
rename from litescope/software/driver/la.py
rename to litescope/software/driver/logic_analyzer.py
index 10083fc..2942b3a 100644
--- a/litescope/software/driver/la.py
+++ b/litescope/software/driver/logic_analyzer.py
@@ -5,7 +5,7 @@ from litescope.software.driver.truthtable import *
 
 import csv
 
-class LiteScopeLADriver():
+class LiteScopeLogicAnalyzerDriver():
     def __init__(self, regs, name, config_csv=None, clk_freq=None, debug=False):
         self.regs = regs
         self.name = name