From 795d70011bcbc83ace461f87bc4664d0f7d15e5b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec <florent@enjoy-digital.fr> Date: Thu, 19 Jan 2017 04:58:04 +0100 Subject: [PATCH] test: use csr write/read functions and switch to python unittest --- test/Makefile | 11 +---------- test/analyzer_tb.py | 45 ------------------------------------------- test/dump_tb.py | 24 ----------------------- test/test_analyzer.py | 44 ++++++++++++++++++++++++++++++++++++++++++ test/test_dump.py | 28 +++++++++++++++++++++++++++ 5 files changed, 73 insertions(+), 79 deletions(-) delete mode 100755 test/analyzer_tb.py delete mode 100755 test/dump_tb.py create mode 100644 test/test_analyzer.py create mode 100644 test/test_dump.py diff --git a/test/Makefile b/test/Makefile index 85e6a32..0b2ae02 100644 --- a/test/Makefile +++ b/test/Makefile @@ -3,18 +3,9 @@ PYTHON = python3 CMD = PYTHONPATH=$(COREDIR) $(PYTHON) -dump_tb: - $(CMD) dump_tb.py - -analyzer_tb: - $(PYTHON) analyzer_tb.py - example_designs: cd ../example_designs && $(PYTHON) make.py -t simple -p de0nano -Ob run False build-bitstream cd ../example_designs && $(PYTHON) make.py -t simple -p kc705 -Ob run False build-bitstream cd ../example_designs && $(PYTHON) make.py -t core build-core -all: dump_tb analyzer_tb example_designs - -clean: - rm -f dump.* +all: example_designs diff --git a/test/analyzer_tb.py b/test/analyzer_tb.py deleted file mode 100755 index 2e6317c..0000000 --- a/test/analyzer_tb.py +++ /dev/null @@ -1,45 +0,0 @@ -#!/usr/bin/env python3 -from litex.gen import * - -from litescope import LiteScopeAnalyzer - -class TB(Module): - def __init__(self): - counter = Signal(16) - self.sync += counter.eq(counter + 1) - - self.submodules.analyzer = LiteScopeAnalyzer(counter, 512) - -def main_generator(dut): - yield dut.analyzer.frontend.trigger.value.storage.eq(0x0080) - yield dut.analyzer.frontend.trigger.mask.storage.eq(0xfff0) - yield dut.analyzer.frontend.subsampler.value.storage.eq(2) - yield - yield dut.analyzer.storage.length.storage.eq(256) - yield dut.analyzer.storage.offset.storage.eq(8) - for i in range(16): - yield - yield dut.analyzer.storage.start.re.eq(1) - yield - yield dut.analyzer.storage.start.re.eq(0) - yield - while not (yield dut.analyzer.storage.idle.status): - yield - data = [] - while (yield dut.analyzer.storage.mem_valid.status): - data.append((yield dut.analyzer.storage.mem_data.status)) - yield dut.analyzer.storage.mem_ready.re.eq(1) - yield dut.analyzer.storage.mem_ready.r.eq(1) - yield - yield dut.analyzer.storage.mem_ready.re.eq(0) - yield dut.analyzer.storage.mem_ready.r.eq(0) - yield - - print(data) - print(len(data)) - -if __name__ == "__main__": - tb = TB() - generators = {"sys" : [main_generator(tb)]} - clocks = {"sys": 10} - run_simulation(tb, generators, clocks, vcd_name="sim.vcd") diff --git a/test/dump_tb.py b/test/dump_tb.py deleted file mode 100755 index abff5a1..0000000 --- a/test/dump_tb.py +++ /dev/null @@ -1,24 +0,0 @@ -from litescope.software.dump import * - -print("creating dump...") -dump = Dump() -for i in range(4): - dump.add(DumpVariable("foo"+str(i), 2**i, [j for j in range(256)])) -pi = 3.1415 -from math import cos, sin -dump.add(DumpVariable("sinus", 8, [128+128*sin(j/(2*pi*16)) for j in range(1024)])) -dump.add(DumpVariable("cosinus", 8, [128+128*cos(j/(2*pi*16)) for j in range(1024)])) - -print("csv export test") -CSVDump(dump).write("dump.csv") - -print("python export test...") -PythonDump(dump).write("dump.py") - -print("sigrok export/import test...") -SigrokDump(dump).write("dump.sr") -SigrokDump(dump).read("dump.sr") -SigrokDump(dump).write("dump.sr") - -print("vcd export test...") -VCDDump(dump).write("dump.vcd") \ No newline at end of file diff --git a/test/test_analyzer.py b/test/test_analyzer.py new file mode 100644 index 0000000..10343e3 --- /dev/null +++ b/test/test_analyzer.py @@ -0,0 +1,44 @@ +import unittest + +from litex.gen import * + +from litescope import LiteScopeAnalyzer + + +class DUT(Module): + def __init__(self): + counter = Signal(16) + self.sync += counter.eq(counter + 1) + + self.submodules.analyzer = LiteScopeAnalyzer(counter, 512) + + +def main_generator(dut): + yield from dut.analyzer.frontend.trigger.value.write(0x0080) + yield from dut.analyzer.frontend.trigger.mask.write(0xfff0) + yield from dut.analyzer.frontend.subsampler.value.write(2) + yield + yield from dut.analyzer.storage.length.write(256) + yield from dut.analyzer.storage.offset.write(8) + for i in range(16): + yield + yield from dut.analyzer.storage.start.write(1) + yield + while not (yield from dut.analyzer.storage.idle.read()): + yield + data = [] + while (yield from dut.analyzer.storage.mem_valid.read()): + data.append((yield from dut.analyzer.storage.mem_data.read())) + yield from dut.analyzer.storage.mem_ready.write(1) + yield + + print(data) + print(len(data)) + + +class TestAnalyzer(unittest.TestCase): + def test(self): + dut = DUT() + generators = {"sys" : [main_generator(dut)]} + clocks = {"sys": 10} + run_simulation(dut, generators, clocks, vcd_name="sim.vcd") diff --git a/test/test_dump.py b/test/test_dump.py new file mode 100644 index 0000000..d1998ae --- /dev/null +++ b/test/test_dump.py @@ -0,0 +1,28 @@ +import unittest + +from litescope.software.dump import * + +class TestDump(unittest.TestCase): + def test(self): + print("creating dump...") + dump = Dump() + for i in range(4): + dump.add(DumpVariable("foo"+str(i), 2**i, [j for j in range(256)])) + pi = 3.1415 + from math import cos, sin + dump.add(DumpVariable("sinus", 8, [128+128*sin(j/(2*pi*16)) for j in range(1024)])) + dump.add(DumpVariable("cosinus", 8, [128+128*cos(j/(2*pi*16)) for j in range(1024)])) + + print("csv export test") + CSVDump(dump).write("dump.csv") + + print("python export test...") + PythonDump(dump).write("dump.py") + + print("sigrok export/import test...") + SigrokDump(dump).write("dump.sr") + SigrokDump(dump).read("dump.sr") + SigrokDump(dump).write("dump.sr") + + print("vcd export test...") + VCDDump(dump).write("dump.vcd") \ No newline at end of file