diff --git a/example_designs/make.py b/example_designs/make.py
index 0ba1de7..ca97087 100644
--- a/example_designs/make.py
+++ b/example_designs/make.py
@@ -168,8 +168,8 @@ RLE: {}
         soc_fragment = soc.get_fragment()
         platform.finalize(soc_fragment)
         so = {
-            NoRetiming:             XilinxNoRetiming,
-            MultiReg:               XilinxMultiReg,
+            NoRetiming:             XilinxNoRetimingVivado,
+            MultiReg:               XilinxMultiRegVivado,
             AsyncResetSynchronizer: XilinxAsyncResetSynchronizer
         }
         v_output = platform.get_verilog(soc_fragment, name="litescope", special_overrides=so)
diff --git a/test/Makefile b/test/Makefile
index 0081b9f..27b963a 100644
--- a/test/Makefile
+++ b/test/Makefile
@@ -11,5 +11,7 @@ example_designs:
 	cd ../example_designs && $(PYTHON) make.py -t simple -p kc705 -Ob run False build-bitstream
 	cd ../example_designs && $(PYTHON) make.py -t core build-core
 
+all: dump_tb example_designs
+
 clean:
 	rm -f dump.*