example_designs: use new Vivado special overrides
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parent
6d975fe388
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7af786e47e
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@ -168,8 +168,8 @@ RLE: {}
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soc_fragment = soc.get_fragment()
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soc_fragment = soc.get_fragment()
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platform.finalize(soc_fragment)
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platform.finalize(soc_fragment)
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so = {
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so = {
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NoRetiming: XilinxNoRetiming,
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NoRetiming: XilinxNoRetimingVivado,
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MultiReg: XilinxMultiReg,
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MultiReg: XilinxMultiRegVivado,
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AsyncResetSynchronizer: XilinxAsyncResetSynchronizer
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AsyncResetSynchronizer: XilinxAsyncResetSynchronizer
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}
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}
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v_output = platform.get_verilog(soc_fragment, name="litescope", special_overrides=so)
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v_output = platform.get_verilog(soc_fragment, name="litescope", special_overrides=so)
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@ -11,5 +11,7 @@ example_designs:
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cd ../example_designs && $(PYTHON) make.py -t simple -p kc705 -Ob run False build-bitstream
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cd ../example_designs && $(PYTHON) make.py -t simple -p kc705 -Ob run False build-bitstream
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cd ../example_designs && $(PYTHON) make.py -t core build-core
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cd ../example_designs && $(PYTHON) make.py -t core build-core
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all: dump_tb example_designs
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clean:
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clean:
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rm -f dump.*
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rm -f dump.*
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