From 7c1c62e34a9b0404dff90f19f2e9b4428817d95e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 31 Aug 2018 08:34:09 +0200 Subject: [PATCH] README: update and rename example_designs to examples --- README | 23 ++++++++----------- example_designs/build/.keep_me | 0 {example_designs => examples}/make.py | 0 .../targets/__init__.py | 0 {example_designs => examples}/targets/core.py | 0 .../targets/simple.py | 0 .../test/test_analyzer_counter.py | 0 .../test/test_analyzer_wishbone.py | 0 .../test/test_identifier.py | 0 {example_designs => examples}/test/test_io.py | 0 setup.py | 2 +- test/Makefile | 10 ++++---- 12 files changed, 15 insertions(+), 20 deletions(-) delete mode 100644 example_designs/build/.keep_me rename {example_designs => examples}/make.py (100%) rename {example_designs => examples}/targets/__init__.py (100%) rename {example_designs => examples}/targets/core.py (100%) rename {example_designs => examples}/targets/simple.py (100%) rename {example_designs => examples}/test/test_analyzer_counter.py (100%) rename {example_designs => examples}/test/test_analyzer_wishbone.py (100%) rename {example_designs => examples}/test/test_identifier.py (100%) rename {example_designs => examples}/test/test_io.py (100%) diff --git a/README b/README index a3908af..0421732 100644 --- a/README +++ b/README @@ -18,27 +18,22 @@ LiteScope is part of LiteX libraries whose aims are to lower entry level of complex FPGA cores by providing simple, elegant and efficient implementations of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller... -Since Python is used to describe the HDL, the core is highly and easily -configurable. - -LiteScope is built using LiteX and uses technologies developed in partnership with -M-Labs Ltd: - - Migen enables generating HDL with Python in an efficient way. - - MiSoC provides the basic blocks to build a powerful and small footprint SoC. +Using Migen to describe the HDL allows the core to be highly and easily configurable. LiteScope can be used as LiteX library or can be integrated with your standard design flow by generating the verilog rtl that you will use as a standard core. [> Features ----------- -- IO peek and poke with LiteScopeIO +- IO peek and poke with LiteScopeIO. - Logic analyser with LiteScopeAnalyzer: - - Subsampling - - Data storage in block rams + - Subsampling. + - Data storage in Block RAM. + - Configurable triggers. - Bridges: - - UART2Wishbone (provided by LiteX) - - Ethernet2Wishbone ("Etherbone") (provided by LiteEth) - - PCIe2Wishbone (provided by LitePCIe) + - UART <--> Wishbone (provided by LiteX) + - Ethernet <--> Wishbone ("Etherbone") (provided by LiteEth) + - PCIe <--> Wishbone (provided by LitePCIe) - Exports formats: .vcd, .sr(sigrok), .csv, .py, etc... [> Proven @@ -68,7 +63,7 @@ enjoy-digital.fr. python3 setup.py develop cd .. -3. TODO: add/describe example design(s) +3. TODO: add/describe examples [> Tests -------- diff --git a/example_designs/build/.keep_me b/example_designs/build/.keep_me deleted file mode 100644 index e69de29..0000000 diff --git a/example_designs/make.py b/examples/make.py similarity index 100% rename from example_designs/make.py rename to examples/make.py diff --git a/example_designs/targets/__init__.py b/examples/targets/__init__.py similarity index 100% rename from example_designs/targets/__init__.py rename to examples/targets/__init__.py diff --git a/example_designs/targets/core.py b/examples/targets/core.py similarity index 100% rename from example_designs/targets/core.py rename to examples/targets/core.py diff --git a/example_designs/targets/simple.py b/examples/targets/simple.py similarity index 100% rename from example_designs/targets/simple.py rename to examples/targets/simple.py diff --git a/example_designs/test/test_analyzer_counter.py b/examples/test/test_analyzer_counter.py similarity index 100% rename from example_designs/test/test_analyzer_counter.py rename to examples/test/test_analyzer_counter.py diff --git a/example_designs/test/test_analyzer_wishbone.py b/examples/test/test_analyzer_wishbone.py similarity index 100% rename from example_designs/test/test_analyzer_wishbone.py rename to examples/test/test_analyzer_wishbone.py diff --git a/example_designs/test/test_identifier.py b/examples/test/test_identifier.py similarity index 100% rename from example_designs/test/test_identifier.py rename to examples/test/test_identifier.py diff --git a/example_designs/test/test_io.py b/examples/test/test_io.py similarity index 100% rename from example_designs/test/test_io.py rename to examples/test/test_io.py diff --git a/setup.py b/setup.py index 43ee49f..3cc8bab 100755 --- a/setup.py +++ b/setup.py @@ -31,6 +31,6 @@ setup( "Operating System :: OS Independent", "Programming Language :: Python", ], - packages=find_packages(exclude=("test*", "sim*", "doc*", "example_designs*")), + packages=find_packages(exclude=("test*", "sim*", "doc*", "examples*")), include_package_data=True, ) diff --git a/test/Makefile b/test/Makefile index 0b2ae02..c4dbfee 100644 --- a/test/Makefile +++ b/test/Makefile @@ -3,9 +3,9 @@ PYTHON = python3 CMD = PYTHONPATH=$(COREDIR) $(PYTHON) -example_designs: - cd ../example_designs && $(PYTHON) make.py -t simple -p de0nano -Ob run False build-bitstream - cd ../example_designs && $(PYTHON) make.py -t simple -p kc705 -Ob run False build-bitstream - cd ../example_designs && $(PYTHON) make.py -t core build-core +examples: + cd ../examples && $(PYTHON) make.py -t simple -p de0nano -Ob run False build-bitstream + cd ../examples && $(PYTHON) make.py -t simple -p kc705 -Ob run False build-bitstream + cd ../examples && $(PYTHON) make.py -t core build-core -all: example_designs +all: examples