README: update and rename example_designs to examples

This commit is contained in:
Florent Kermarrec 2018-08-31 08:34:09 +02:00
parent 3567b68981
commit 7c1c62e34a
12 changed files with 15 additions and 20 deletions

23
README
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@ -18,27 +18,22 @@ LiteScope is part of LiteX libraries whose aims are to lower entry level of
complex FPGA cores by providing simple, elegant and efficient implementations complex FPGA cores by providing simple, elegant and efficient implementations
of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller... of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
Since Python is used to describe the HDL, the core is highly and easily Using Migen to describe the HDL allows the core to be highly and easily configurable.
configurable.
LiteScope is built using LiteX and uses technologies developed in partnership with
M-Labs Ltd:
- Migen enables generating HDL with Python in an efficient way.
- MiSoC provides the basic blocks to build a powerful and small footprint SoC.
LiteScope can be used as LiteX library or can be integrated with your standard LiteScope can be used as LiteX library or can be integrated with your standard
design flow by generating the verilog rtl that you will use as a standard core. design flow by generating the verilog rtl that you will use as a standard core.
[> Features [> Features
----------- -----------
- IO peek and poke with LiteScopeIO - IO peek and poke with LiteScopeIO.
- Logic analyser with LiteScopeAnalyzer: - Logic analyser with LiteScopeAnalyzer:
- Subsampling - Subsampling.
- Data storage in block rams - Data storage in Block RAM.
- Configurable triggers.
- Bridges: - Bridges:
- UART2Wishbone (provided by LiteX) - UART <--> Wishbone (provided by LiteX)
- Ethernet2Wishbone ("Etherbone") (provided by LiteEth) - Ethernet <--> Wishbone ("Etherbone") (provided by LiteEth)
- PCIe2Wishbone (provided by LitePCIe) - PCIe <--> Wishbone (provided by LitePCIe)
- Exports formats: .vcd, .sr(sigrok), .csv, .py, etc... - Exports formats: .vcd, .sr(sigrok), .csv, .py, etc...
[> Proven [> Proven
@ -68,7 +63,7 @@ enjoy-digital.fr.
python3 setup.py develop python3 setup.py develop
cd .. cd ..
3. TODO: add/describe example design(s) 3. TODO: add/describe examples
[> Tests [> Tests
-------- --------

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@ -31,6 +31,6 @@ setup(
"Operating System :: OS Independent", "Operating System :: OS Independent",
"Programming Language :: Python", "Programming Language :: Python",
], ],
packages=find_packages(exclude=("test*", "sim*", "doc*", "example_designs*")), packages=find_packages(exclude=("test*", "sim*", "doc*", "examples*")),
include_package_data=True, include_package_data=True,
) )

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@ -3,9 +3,9 @@ PYTHON = python3
CMD = PYTHONPATH=$(COREDIR) $(PYTHON) CMD = PYTHONPATH=$(COREDIR) $(PYTHON)
example_designs: examples:
cd ../example_designs && $(PYTHON) make.py -t simple -p de0nano -Ob run False build-bitstream cd ../examples && $(PYTHON) make.py -t simple -p de0nano -Ob run False build-bitstream
cd ../example_designs && $(PYTHON) make.py -t simple -p kc705 -Ob run False build-bitstream cd ../examples && $(PYTHON) make.py -t simple -p kc705 -Ob run False build-bitstream
cd ../example_designs && $(PYTHON) make.py -t core build-core cd ../examples && $(PYTHON) make.py -t core build-core
all: example_designs all: examples