From 7f4dc390d93bf0ade7cc8d62d1f357593e89e5c7 Mon Sep 17 00:00:00 2001
From: "kees.jongenburger" <kees.jongenburger@gmail.com>
Date: Fri, 14 Jun 2019 16:57:33 +0200
Subject: [PATCH] Add functionality to flatten values that are sampled using a
 serdes.

This code add some functionality to flatten the values back from
the serial to parallel conversion that happens when sampling
using the serdes.
---
 litescope/software/driver/analyzer.py |  7 +++++--
 litescope/software/dump/common.py     | 28 ++++++++++++++++++++-------
 2 files changed, 26 insertions(+), 9 deletions(-)

diff --git a/litescope/software/driver/analyzer.py b/litescope/software/driver/analyzer.py
index 563e327..ef9f375 100644
--- a/litescope/software/driver/analyzer.py
+++ b/litescope/software/driver/analyzer.py
@@ -126,7 +126,7 @@ class LiteScopeAnalyzerDriver:
             print("")
         return self.data
 
-    def save(self, filename, samplerate=None):
+    def save(self, filename, samplerate=None, flatten=False):
         if self.debug:
             print("[writing to " + filename + "]...")
         name, ext = os.path.splitext(filename)
@@ -140,7 +140,10 @@ class LiteScopeAnalyzerDriver:
             dump = SigrokDump(samplerate=samplerate)
         else:
             raise NotImplementedError
-        dump.add_from_layout(self.layouts[self.group], self.data)
+        if not flatten:
+            dump.add_from_layout(self.layouts[self.group], self.data)
+        else:
+            dump.add_from_layout_flatten(self.layouts[self.group], self.data)
         dump.write(filename)
 
     def get_instant_value(self, group, name):
diff --git a/litescope/software/dump/common.py b/litescope/software/dump/common.py
index d93f027..183e1b6 100644
--- a/litescope/software/dump/common.py
+++ b/litescope/software/dump/common.py
@@ -48,8 +48,8 @@ class DumpData(list):
 
 class DumpVariable:
     def __init__(self, name, width, values=[]):
-        self.width = width
         self.name = name
+        self.width = width
         self.values = [int(v)%2**width for v in values]
 
     def __len__(self):
@@ -64,12 +64,26 @@ class Dump:
         self.variables.append(variable)
 
     def add_from_layout(self, layout, variable):
-        i = 0
-        for s, n in layout:
-            values = variable[i:i+n]
-            values2x = [values[j//2] for j in range(len(values)*2)]
-            self.add(DumpVariable(s, n, values2x))
-            i += n
+        offset = 0
+        for name, sample_width in layout:
+            values = variable[offset:offset+sample_width]
+            values2x = [values[i//2] for i in range(len(values)*2)]
+            self.add(DumpVariable(name, sample_width, values2x))
+            offset += sample_width
+        self.add(DumpVariable("scope_clk", 1, [1, 0]*(len(self)//2)))
+
+    def add_from_layout_flatten(self, layout, variable):
+        offset = 0
+        for name, sample_width in layout:
+            # The samples from the logic analyzer end up in an array of size sample size
+            # and have n (number of channel) bits. The following does a bit slice on the array
+            # elements (implemented above)
+            values = variable[offset:offset+sample_width]
+            values_flatten = [values[i//sample_width] >> (i % sample_width ) & 1 for i in range(len(values)*sample_width)]
+            self.add(DumpVariable(name, 1, values_flatten))
+            offset += sample_width
+        # the clock.. might need some more love here. the clock pattern probably should be sample_width wide
+        # e.g. 11110000 and not 10101010
         self.add(DumpVariable("scope_clk", 1, [1, 0]*(len(self)//2)))
 
     def __len__(self):