From 824985cdd322d1eb907db03e91d6085c53da782d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Boczar?= Date: Tue, 23 Mar 2021 09:58:52 +0100 Subject: [PATCH] litescope/core: add option to register input signals to cut timings --- litescope/core.py | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/litescope/core.py b/litescope/core.py index ea285f9..7d4fa62 100644 --- a/litescope/core.py +++ b/litescope/core.py @@ -226,7 +226,7 @@ class _Storage(Module, AutoCSR): class LiteScopeAnalyzer(Module, AutoCSR): - def __init__(self, groups, depth, clock_domain="sys", trigger_depth=16, csr_csv="analyzer.csv"): + def __init__(self, groups, depth, clock_domain="sys", trigger_depth=16, register=0, csr_csv="analyzer.csv"): self.groups = groups = self.format_groups(groups) self.depth = depth @@ -242,10 +242,16 @@ class LiteScopeAnalyzer(Module, AutoCSR): # Mux self.submodules.mux = _Mux(data_width, len(groups)) + sd = getattr(self.sync, clock_domain) for i, signals in groups.items(): + s = Cat(signals) + for _ in range(register): + s_d = Signal(len(s)) + sd += s_d.eq(s) + s = s_d self.comb += [ self.mux.sinks[i].valid.eq(1), - self.mux.sinks[i].data.eq(Cat(signals)) + self.mux.sinks[i].data.eq(s) ] # Frontend