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example_designs: change the way we build cores (ensure consistent IO naming)

This commit is contained in:
Florent Kermarrec 2015-12-27 15:42:37 +01:00
parent 378272d9e2
commit 83e06cad80
2 changed files with 10 additions and 18 deletions
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10
example_designs/make.py
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@ -45,7 +45,7 @@ This program builds and/or loads LiteScope components.
One or several actions can be specified: One or several actions can be specified:
clean delete previous build(s). clean delete previous build(s).
build-rtl build verilog rtl. build-core build verilog core.
build-bitstream build-bitstream build FPGA bitstream. build-bitstream build-bitstream build FPGA bitstream.
build-csr-csv save CSR map into CSV file. build-csr-csv save CSR map into CSV file.
@ -165,16 +165,14 @@ RLE: {}
write_to_file(args.csr_csv, csr_csv) write_to_file(args.csr_csv, csr_csv)
if actions["build-core"]: if actions["build-core"]:
ios = soc.get_ios() soc_fragment = soc.get_fragment()
if not isinstance(soc, _Fragment): platform.finalize(soc_fragment)
soc = soc.get_fragment()
platform.finalize(soc)
so = { so = {
NoRetiming: XilinxNoRetiming, NoRetiming: XilinxNoRetiming,
MultiReg: XilinxMultiReg, MultiReg: XilinxMultiReg,
AsyncResetSynchronizer: XilinxAsyncResetSynchronizer AsyncResetSynchronizer: XilinxAsyncResetSynchronizer
} }
v_output = verilog.convert(soc, ios, special_overrides=so) v_output = platform.get_verilog(soc_fragment, name="litescope", special_overrides=so)
v_output.write("build/litescope.v") v_output.write("build/litescope.v")
if actions["build-bitstream"]: if actions["build-bitstream"]:

18
example_designs/targets/core.py
View File

@ -15,8 +15,8 @@ from litescope.frontend.logic_analyzer import LiteScopeLogicAnalyzer
_io = [ _io = [
("sys_clk", 0, Pins(1)), ("sys_clock", 0, Pins(1)),
("sys_rst", 1, Pins(1)), ("sys_reset", 1, Pins(1)),
("serial", 0, ("serial", 0,
Subsignal("tx", Pins(1)), Subsignal("tx", Pins(1)),
Subsignal("rx", Pins(1)), Subsignal("rx", Pins(1)),
@ -42,8 +42,11 @@ class Core(SoCCore):
csr_map.update(SoCCore.csr_map) csr_map.update(SoCCore.csr_map)
def __init__(self, platform, clk_freq=100*1000000): def __init__(self, platform, clk_freq=100*1000000):
self.clk_freq = clk_freq
self.clock_domains.cd_sys = ClockDomain("sys") self.clock_domains.cd_sys = ClockDomain("sys")
self.comb += [
self.cd_sys.clk.eq(platform.request("sys_clock")),
self.cd_sys.rst.eq(platform.request("sys_reset"))
]
SoCCore.__init__(self, platform, clk_freq, SoCCore.__init__(self, platform, clk_freq,
cpu_type=None, cpu_type=None,
csr_data_width=32, csr_data_width=32,
@ -58,13 +61,4 @@ class Core(SoCCore):
self.submodules.logic_analyzer = LiteScopeLogicAnalyzer((self.bus), 512, with_rle=True, with_subsampler=True) self.submodules.logic_analyzer = LiteScopeLogicAnalyzer((self.bus), 512, with_rle=True, with_subsampler=True)
self.logic_analyzer.trigger.add_port(LiteScopeTerm(self.logic_analyzer.dw)) self.logic_analyzer.trigger.add_port(LiteScopeTerm(self.logic_analyzer.dw))
def get_ios(self):
ios = set()
ios = ios.union({self.cd_sys.clk,
self.cd_sys.rst})
ios = ios.union({self.platform.lookup_request("serial").rx,
self.platform.lookup_request("serial").tx})
ios = ios.union({self.bus})
return ios
default_subtarget = Core default_subtarget = Core