From 8f88088f63514ae0538982087bd65b8461515cff Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 16 Mar 2016 20:10:09 +0100 Subject: [PATCH] global: use valid/ready/last signals instead of stb/ack/eop (similar to AXI) --- litescope/core/port.py | 12 ++--- litescope/core/storage.py | 50 ++++++++++----------- litescope/core/trigger.py | 10 ++--- litescope/frontend/logic_analyzer.py | 4 +- litescope/software/driver/logic_analyzer.py | 4 +- 5 files changed, 40 insertions(+), 40 deletions(-) diff --git a/litescope/core/port.py b/litescope/core/port.py index 75376d4..bf21b8c 100644 --- a/litescope/core/port.py +++ b/litescope/core/port.py @@ -13,9 +13,9 @@ class LiteScopeTermUnit(Module): # # # self.comb += [ - source.stb.eq(sink.stb), + source.valid.eq(sink.valid), source.hit.eq((sink.data & self.mask) == self.trig), - sink.ack.eq(source.ack) + sink.ready.eq(source.ready) ] @@ -45,9 +45,9 @@ class LiteScopeRangeDetectorUnit(Module): # # # self.comb += [ - source.stb.eq(sink.stb), + source.valid.eq(sink.valid), source.hit.eq((sink.data >= self.low) & (sink.data <= self.high)), - sink.ack.eq(source.ack) + sink.ready.eq(source.ready) ] @@ -90,8 +90,8 @@ class LiteScopeEdgeDetectorUnit(Module): self.comb += both.eq(self.both_mask & (rising | falling)) self.comb += [ - source.stb.eq(sink.stb & self.buffer.q.stb), - self.buffer.q.ack.eq(source.ack), + source.valid.eq(sink.valid & self.buffer.q.valid), + self.buffer.q.ready.eq(source.ready), source.hit.eq((rising | falling | both) != 0) ] diff --git a/litescope/core/storage.py b/litescope/core/storage.py index ae0fe1c..89497a1 100644 --- a/litescope/core/storage.py +++ b/litescope/core/storage.py @@ -24,9 +24,9 @@ class LiteScopeSubSamplerUnit(Module): self.comb += [ done.eq(counter >= self.value), sink.connect(source), - source.stb.eq(sink.stb & done), - counter_ce.eq(source.ack), - counter_reset.eq(source.stb & source.ack & done) + source.valid.eq(sink.valid & done), + counter_ce.eq(source.ready), + counter_reset.eq(source.valid & source.ready & done) ] @@ -69,7 +69,7 @@ class LiteScopeRunLengthEncoderUnit(Module): change = Signal() self.comb += change.eq( - sink.stb & + sink.valid & (sink.data != buf.source.data) ) @@ -77,23 +77,23 @@ class LiteScopeRunLengthEncoderUnit(Module): fsm.act("BYPASS", buf.source.connect(source), counter_reset.eq(1), - If(sink.stb & ~change, + If(sink.valid & ~change, If(self.enable, NextState("COUNT") ) ) ) fsm.act("COUNT", - buf.source.ack.eq(1), - counter_ce.eq(sink.stb), + buf.source.ready.eq(1), + counter_ce.eq(sink.valid), If(~self.enable, NextState("BYPASS") ).Elif(change | counter_done, - source.stb.eq(1), + source.valid.eq(1), source.data[:len(counter)].eq(counter), source.data[-1].eq(1), # Set RLE bit - buf.source.ack.eq(source.ack), - If(source.ack, + buf.source.ready.eq(source.ready), + If(source.ready, NextState("BYPASS") ) ) @@ -136,7 +136,7 @@ class LiteScopeRecorderUnit(Module): fsm = FSM(reset_state="IDLE") self.submodules += fsm self.comb += [ - self.source.stb.eq(fifo.source.stb), + self.source.valid.eq(fifo.source.valid), self.source.data.eq(fifo.source.data) ] fsm.act("IDLE", @@ -145,31 +145,31 @@ class LiteScopeRecorderUnit(Module): NextState("PRE_HIT_RECORDING"), fifo.reset.eq(1), ), - fifo.source.ack.eq(self.source.ack) + fifo.source.ready.eq(self.source.ready) ) fsm.act("PRE_HIT_RECORDING", - fifo.sink.stb.eq(data_sink.stb), + fifo.sink.valid.eq(data_sink.valid), fifo.sink.data.eq(data_sink.data), - data_sink.ack.eq(fifo.sink.ack), + data_sink.ready.eq(fifo.sink.ready), - fifo.source.ack.eq(fifo.level >= self.offset), - If(trigger_sink.stb & trigger_sink.hit, + fifo.source.ready.eq(fifo.level >= self.offset), + If(trigger_sink.valid & trigger_sink.hit, NextState("POST_HIT_RECORDING") ) ) fsm.act("POST_HIT_RECORDING", self.post_hit.eq(1), If(self.qualifier, - fifo.sink.stb.eq(trigger_sink.stb & + fifo.sink.valid.eq(trigger_sink.valid & trigger_sink.hit & - data_sink.stb) + data_sink.valid) ).Else( - fifo.sink.stb.eq(data_sink.stb) + fifo.sink.valid.eq(data_sink.valid) ), fifo.sink.data.eq(data_sink.data), - data_sink.ack.eq(fifo.sink.ack), + data_sink.ready.eq(fifo.sink.ready), - If(~fifo.sink.ack | (fifo.level >= self.length), + If(~fifo.sink.ready | (fifo.level >= self.length), NextState("IDLE") ) ) @@ -185,8 +185,8 @@ class LiteScopeRecorder(LiteScopeRecorderUnit, AutoCSR): self._offset = CSRStorage(bits_for(depth)) self._done = CSRStatus() - self._source_stb = CSRStatus() - self._source_ack = CSR() + self._source_valid = CSRStatus() + self._source_ready = CSR() self._source_data = CSRStatus(dw) # # # @@ -198,7 +198,7 @@ class LiteScopeRecorder(LiteScopeRecorderUnit, AutoCSR): self.offset.eq(self._offset.storage), self._done.status.eq(self.done), - self._source_stb.status.eq(self.source.stb), + self._source_valid.status.eq(self.source.valid), self._source_data.status.eq(self.source.data), - self.source.ack.eq(self._source_ack.re) + self.source.ready.eq(self._source_ready.re) ] diff --git a/litescope/core/trigger.py b/litescope/core/trigger.py index 73126d1..8165630 100644 --- a/litescope/core/trigger.py +++ b/litescope/core/trigger.py @@ -33,11 +33,11 @@ class LiteScopeSumUnit(Module, AutoCSR): # drive source self.comb += [ - source.stb.eq(reduce(and_, [sink.stb for sink in sinks])), + source.valid.eq(reduce(and_, [sink.valid for sink in sinks])), source.hit.eq(lut.dat_r) ] for i, sink in enumerate(sinks): - self.comb += sink.ack.eq(sink.stb & source.ack) + self.comb += sink.ready.eq(sink.valid & source.ready) class LiteScopeSum(LiteScopeSumUnit, AutoCSR): @@ -70,11 +70,11 @@ class LiteScopeTrigger(Module, AutoCSR): def do_finalize(self): self.submodules.sum = LiteScopeSum(len(self.ports)) for i, port in enumerate(self.ports): - # Note: port's ack is not used and supposed to be always 1 + # Note: port's ready is not used and supposed to be always 1 self.comb += [ - port.sink.stb.eq(self.sink.stb), + port.sink.valid.eq(self.sink.valid), port.sink.data.eq(self.sink.data), - self.sink.ack.eq(1), + self.sink.ready.eq(1), port.source.connect(self.sum.sinks[i]) ] self.comb += self.sum.source.connect(self.source) diff --git a/litescope/frontend/logic_analyzer.py b/litescope/frontend/logic_analyzer.py index 5199788..8e7dca6 100644 --- a/litescope/frontend/logic_analyzer.py +++ b/litescope/frontend/logic_analyzer.py @@ -25,7 +25,7 @@ class LiteScopeLogicAnalyzer(Module, AutoCSR): self.sink = stream.Endpoint(data_layout(self.dw)) self.comb += [ - self.sink.stb.eq(1), + self.sink.valid.eq(1), self.sink.data.eq(self.data) ] @@ -55,7 +55,7 @@ class LiteScopeLogicAnalyzer(Module, AutoCSR): # connect trigger self.comb += [ - self.trigger.sink.stb.eq(sink.stb), + self.trigger.sink.valid.eq(sink.valid), self.trigger.sink.data.eq(sink.data), ] diff --git a/litescope/software/driver/logic_analyzer.py b/litescope/software/driver/logic_analyzer.py index 2302b01..94170a8 100644 --- a/litescope/software/driver/logic_analyzer.py +++ b/litescope/software/driver/logic_analyzer.py @@ -113,9 +113,9 @@ class LiteScopeLogicAnalyzerDriver(): def upload(self): if self.debug: print("uploading") - while self.recorder_source_stb.read(): + while self.recorder_source_valid.read(): self.data.append(self.recorder_source_data.read()) - self.recorder_source_ack.write(1) + self.recorder_source_ready.write(1) if self.with_rle: if self.rle_enable.read(): self.data = self.data.decode_rle()