From 92c7af04dbc687954a5301137c6b5c17cf9ed082 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 19 Nov 2015 15:00:18 +0100 Subject: [PATCH] example_designs/targets/core: use new Pins from LiteX (allow int parameters) --- example_designs/targets/core.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/example_designs/targets/core.py b/example_designs/targets/core.py index 5694200..e103a50 100644 --- a/example_designs/targets/core.py +++ b/example_designs/targets/core.py @@ -15,13 +15,13 @@ from litescope.frontend.logic_analyzer import LiteScopeLogicAnalyzer _io = [ - ("sys_clk", 0, Pins("X")), - ("sys_rst", 1, Pins("X")), + ("sys_clk", 0, Pins(1)), + ("sys_rst", 1, Pins(1)), ("serial", 0, - Subsignal("tx", Pins("X")), - Subsignal("rx", Pins("X")), + Subsignal("tx", Pins(1)), + Subsignal("rx", Pins(1)), ), - ("bus", 0, Pins(" ".join(["X" for i in range(128)]))) + ("bus", 0, Pins(128)) ] class CorePlatform(XilinxPlatform):