replace litex.gen imports with migen imports

example_designs/make.py

@@ -7,8 +7,8 @@ import subprocess
 import struct
 import importlib
 
-from litex.gen.fhdl import verilog
-from litex.gen.fhdl.structure import _Fragment
+from migen.fhdl import verilog
+from migen.fhdl.structure import _Fragment
 
 from litex.build.tools import write_to_file
 from litex.build.xilinx.common import *

example_designs/targets/core.py

@@ -1,5 +1,5 @@
-from litex.gen import *
-from litex.gen.genlib.io import CRG
+from migen import *
+from migen.genlib.io import CRG
 
 from targets import *
 

example_designs/targets/simple.py

@@ -1,5 +1,5 @@
-from litex.gen import *
-from litex.gen.genlib.io import CRG
+from migen import *
+from migen.genlib.io import CRG
 
 from litex.soc.integration.soc_core import SoCCore
 from litex.soc.cores.uart import UARTWishboneBridge

litescope/core.py

@@ -1,5 +1,5 @@
-from litex.gen import *
-from litex.gen.genlib.cdc import MultiReg
+from migen import *
+from migen.genlib.cdc import MultiReg
 
 from litex.build.tools import write_to_file
 

litescope/software/driver/analyzer.py

@@ -1,7 +1,8 @@
 import os
 import sys
 
-from litex.gen.fhdl.structure import *
+from migen.fhdl.structure import *
+
 from litescope.software.dump.common import *
 from litescope.software.dump import *
 

test/test_analyzer.py

@@ -1,6 +1,6 @@
 import unittest
 
-from litex.gen import *
+from migen import *
 
 from litescope import LiteScopeAnalyzer