examples: simplify/update

examples/targets/core.py

@@ -2,15 +2,13 @@
 # License: BSD
 
 from migen import *
-from migen.genlib.io import CRG
 
 from targets import *
 
 from litex.build.generic_platform import *
 from litex.build.xilinx.platform import XilinxPlatform
 
-from litex.soc.integration.soc_core import SoCCore
+from litex.soc.integration.soc_core import SoCMini
-from litex.soc.cores.uart import UARTWishboneBridge
 
 from litescope import LiteScopeAnalyzer
 
@@ -25,41 +23,27 @@ _io = [
     ("bus", 0, Pins(128))
 ]
 
+
 class CorePlatform(XilinxPlatform):
     name = "core"
-    default_clk_name = "sys_clk"
     def __init__(self):
         XilinxPlatform.__init__(self, "", _io)
 
-    def do_finalize(self, *args, **kwargs):
-        pass
 
-
+class Core(SoCMini):
-class Core(SoCCore):
     platform = CorePlatform()
-    csr_map = {
-        "analyzer":    16
-    }
-    csr_map.update(SoCCore.csr_map)
-
     def __init__(self, platform, clk_freq=100*1000000):
         self.clock_domains.cd_sys = ClockDomain("sys")
         self.comb += [
             self.cd_sys.clk.eq(platform.request("sys_clock")),
             self.cd_sys.rst.eq(platform.request("sys_reset"))
         ]
-        SoCCore.__init__(self, platform, clk_freq,
+        SoCMini.__init__(self, platform, clk_freq, csr_data_width=32,
-            cpu_type=None,
+            with_uart=True, uart_name="bridge",
-            csr_data_width=32,
+            ident="Litescope example design", ident_version=True,
-            with_uart=False,
-            ident="Litescope example design",
-            with_timer=False
         )
-        bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)
-        self.submodules.bridge = bridge
-        self.add_wb_master(bridge.wishbone)
 
-        self.bus = platform.request("bus")
+        self.submodules.analyzer = LiteScopeAnalyzer(platform.request("bus"), 512)
-        self.submodules.analyzer = LiteScopeAnalyzer((self.bus), 512)
+        self.add_csr("analyzer")
 
 default_subtarget = Core

examples/targets/simple.py

@@ -4,65 +4,58 @@
 from migen import *
 from migen.genlib.io import CRG
 
-from litex.soc.integration.soc_core import SoCCore
+from litex.soc.integration.soc_core import SoCMini
-from litex.soc.cores.uart import UARTWishboneBridge
 
 from litescope import LiteScopeIO, LiteScopeAnalyzer
 
+# LiteScope SoC ------------------------------------------------------------------------------------
 
-class LiteScopeSoC(SoCCore):
+class LiteScopeSoC(SoCMini):
-    csr_map = {
-        "io":       16,
-        "analyzer": 17
-    }
-    csr_map.update(SoCCore.csr_map)
-
     def __init__(self, platform):
         sys_clk_freq = int((1e9/platform.default_clk_period))
-        SoCCore.__init__(self, platform, sys_clk_freq,
+
-            cpu_type=None,
+        # SoCMini ----------------------------------------------------------------------------------
-            csr_data_width=32,
+        SoCMini.__init__(self, platform, sys_clk_freq,
-            with_uart=False,
+            csr_data_width = 32,
-            ident="Litescope example design", ident_version=True,
+            with_uart      = True,
-            with_timer=False
+            uart_name      = "bridge",
+            ident          = "Litescope example design",
+            ident_version  = True,
         )
-        # crg
+
+        # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = CRG(platform.request(platform.default_clk_name))
 
-        # bridge
+        # Litescope IO -----------------------------------------------------------------------------
-        bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq, baudrate=115200)
-        self.submodules.bridge = bridge
-        self.add_wb_master(bridge.wishbone)
-
-        # Litescope IO
         self.submodules.io = LiteScopeIO(8)
+        self.add_csr("io")
         for i in range(8):
             try:
                 self.comb += platform.request("user_led", i).eq(self.io.output[i])
             except:
                 pass
 
-        # Litescope Analyzer
+        # Litescope Analyzer -----------------------------------------------------------------------
         analyzer_groups = {}
 
-        # counter group
+        # Counter group
         counter = Signal(16, name_override="counter")
-        zero = Signal(name_override="zero")
+        zero    = Signal(name_override="zero")
         self.sync += counter.eq(counter + 1)
         self.comb += zero.eq(counter == 0)
         analyzer_groups[0] = [
             zero,
-            counter
+            counter,
         ]
 
-        # communication group
+        # Communication group
         analyzer_groups[1] = [
             platform.lookup_request("serial").tx,
             platform.lookup_request("serial").rx,
-            bridge.wishbone
+            self.bus.masters["uart_bridge"],
         ]
 
-        # fsm group
+        # FSM group
         fsm = FSM(reset_state="STATE1")
         self.submodules += fsm
         fsm.act("STATE1",
@@ -72,13 +65,11 @@ class LiteScopeSoC(SoCCore):
             NextState("STATE1")
         )
         analyzer_groups[2] = [
-            fsm
+            fsm,
         ]
 
-        # analyzer
+        # Analyzer
-        self.submodules.analyzer = LiteScopeAnalyzer(analyzer_groups, 512)
+        self.submodules.analyzer = LiteScopeAnalyzer(analyzer_groups, 512, csr_csv="test/analyzer.csv")
-
+        self.add_csr("analyzer")
-    def do_exit(self, vns):
-        self.analyzer.export_csv(vns, "test/analyzer.csv")
 
 default_subtarget = LiteScopeSoC

test/test_examples.py

@@ -16,7 +16,7 @@ class TestExamples(unittest.TestCase):
         os.system("python3 {} -t simple -p de0nano -Ob run False build-bitstream".format(make_script))
         self.assertEqual(os.path.isfile("{}/build/litescopesoc_de0nano.v".format(root_dir)), True)
 
-    def test_simple_705(self):
+    def test_simple_kc705(self):
         os.system("rm -rf {}/build".format(root_dir))
         os.system("python3 {} -t simple -p kc705 -Ob run False build-bitstream".format(make_script))
         self.assertEqual(os.path.isfile("{}/build/litescopesoc_kc705.v".format(root_dir)), True)