From ad4e46c8c6ef9474c40c4248b6cb6a0ec36abc7d Mon Sep 17 00:00:00 2001 From: Christian Klarhorst Date: Fri, 7 Aug 2020 13:56:06 +0200 Subject: [PATCH] Fix: 2 signals in the storage class belong to the wrong clock domain Signals & Domain overview: - self.{offset,length}.storage belong to sys clock - offset, length belong to scope clock - mem belongs to scope clock Therefore, everything that involves mem needs to use offset/length --- litescope/core.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litescope/core.py b/litescope/core.py index 7c42968..a963f50 100644 --- a/litescope/core.py +++ b/litescope/core.py @@ -208,11 +208,11 @@ class _Storage(Module, AutoCSR): If(sink.valid & sink.hit, NextState("RUN") ), - mem.source.ready.eq(mem.level >= self.offset.storage) + mem.source.ready.eq(mem.level >= offset) ) fsm.act("RUN", sink.connect(mem.sink, omit={"hit"}), - If(mem.level >= self.length.storage, + If(mem.level >= length, NextState("IDLE"), ) )