example_design: demonstrate how to use groups, create separate capture for vcd (bus support) and sigrok (no bus support)

This commit is contained in:
Florent Kermarrec 2017-06-22 19:12:33 +02:00
parent 92710208de
commit b57a5f9369
2 changed files with 43 additions and 11 deletions

View File

@ -34,9 +34,36 @@ class LiteScopeSoC(SoCCore):
except:
pass
counter = Signal(16)
# use name override to keep naming in capture
counter = Signal(4, name_override="counter")
counter0 = Signal(name_override="counter0")
counter1 = Signal(name_override="counter1")
counter2 = Signal(name_override="counter2")
counter3 = Signal(name_override="counter3")
self.sync += counter.eq(counter + 1)
self.submodules.analyzer = LiteScopeAnalyzer(counter, 512)
self.comb += [
counter0.eq(counter[0]),
counter1.eq(counter[1]),
counter2.eq(counter[2]),
counter3.eq(counter[3]),
]
# group for vcd capture
vcd_group = [
counter
]
# group for sigrok capture (no bus support)
sigrok_group = [
counter0,
counter1,
counter2,
counter3
]
analyzer_signals = {
0 : vcd_group,
1 : sigrok_group
}
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
def do_exit(self, vns):
self.analyzer.export_csv(vns, "test/analyzer.csv")

View File

@ -6,15 +6,20 @@ wb.open()
# # #
dumps = {
0 : "dump.vcd",
1 : "dump.sr"
}
for group, filename in dumps.items():
analyzer = LiteScopeAnalyzerDriver(wb.regs, "analyzer", debug=True)
analyzer.configure_trigger(cond={"counter1": 0})
analyzer.configure_trigger()
analyzer.configure_subsampler(1)
analyzer.configure_group(group)
analyzer.run(offset=128, length=512)
while not analyzer.done():
pass
analyzer.wait_done()
analyzer.upload()
analyzer.save("dump.vcd")
analyzer.save("dump.sr")
analyzer.save(filename)
# # #