example_design: demonstrate how to use groups, create separate capture for vcd (bus support) and sigrok (no bus support)
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@ -34,9 +34,36 @@ class LiteScopeSoC(SoCCore):
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except:
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pass
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counter = Signal(16)
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# use name override to keep naming in capture
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counter = Signal(4, name_override="counter")
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counter0 = Signal(name_override="counter0")
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counter1 = Signal(name_override="counter1")
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counter2 = Signal(name_override="counter2")
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counter3 = Signal(name_override="counter3")
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self.sync += counter.eq(counter + 1)
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self.submodules.analyzer = LiteScopeAnalyzer(counter, 512)
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self.comb += [
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counter0.eq(counter[0]),
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counter1.eq(counter[1]),
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counter2.eq(counter[2]),
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counter3.eq(counter[3]),
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]
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# group for vcd capture
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vcd_group = [
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counter
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]
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# group for sigrok capture (no bus support)
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sigrok_group = [
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counter0,
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counter1,
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counter2,
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counter3
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]
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analyzer_signals = {
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0 : vcd_group,
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1 : sigrok_group
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}
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self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
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def do_exit(self, vns):
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self.analyzer.export_csv(vns, "test/analyzer.csv")
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@ -6,15 +6,20 @@ wb.open()
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# # #
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dumps = {
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0 : "dump.vcd",
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1 : "dump.sr"
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}
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for group, filename in dumps.items():
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analyzer = LiteScopeAnalyzerDriver(wb.regs, "analyzer", debug=True)
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analyzer.configure_trigger(cond={"counter1": 0})
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analyzer.configure_trigger()
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analyzer.configure_subsampler(1)
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analyzer.configure_group(group)
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analyzer.run(offset=128, length=512)
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while not analyzer.done():
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pass
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analyzer.wait_done()
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analyzer.upload()
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analyzer.save("dump.vcd")
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analyzer.save("dump.sr")
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analyzer.save(filename)
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# # #
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