From bc6c5e35eef3638b5c45ca6d17fcdbf4f3af9b90 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 5 Aug 2020 13:19:02 +0200
Subject: [PATCH] examples: add mininal example on Arty with Etherbone and
 ibus/counter on analyzer.

---
 examples/arty.py                    | 68 +++++++++++++++++++++++++++++
 litescope/software/litescope_cli.py |  4 +-
 2 files changed, 70 insertions(+), 2 deletions(-)
 create mode 100755 examples/arty.py

diff --git a/examples/arty.py b/examples/arty.py
new file mode 100755
index 0000000..b039732
--- /dev/null
+++ b/examples/arty.py
@@ -0,0 +1,68 @@
+#!/usr/bin/env python3
+
+# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
+# License: BSD
+
+# Use:
+# ./arty.py --build --load
+# lxserver --udp (for LiteScope over UDP)
+# litescope_cli: will trigget an immediate capture!
+# litescope_cli --help: list the available trigger option.
+# litescope_cli --list: list the signals that can be used as triggers.
+# litescope_cli -v main_count 128: trigger on count value == 128.
+# litescope_cli -r litescopesoc_cpu_ibus_stb: trigger in ibus_stb rising edge
+# For more information: https://github.com/enjoy-digital/litex/wiki/Use-LiteScope-To-Debug-A-SoC
+
+import os
+import argparse
+
+from migen import *
+
+from litex.boards.platforms import arty
+from litex.boards.targets.arty import *
+
+from litescope import LiteScopeAnalyzer
+
+# LiteScopeSoC -------------------------------------------------------------------------------------
+
+class LiteScopeSoC(BaseSoC):
+    def __init__(self):
+        platform = arty.Platform()
+
+        # BaseSoC ----------------------------------------------------------------------------------
+        BaseSoC.__init__(self,
+            integrated_rom_size = 0x8000,
+            with_etherbone      = True,
+        )
+
+        # LiteScope Analyzer -----------------------------------------------------------------------
+        count = Signal(8)
+        self.sync += count.eq(count + 1)
+        analyzer_signals = [
+            self.cpu.ibus,
+            count,
+        ]
+        self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
+            depth        = 1024,
+            clock_domain = "sys",
+            csr_csv      = "analyzer.csv")
+        self.add_csr("analyzer")
+
+# Build --------------------------------------------------------------------------------------------
+
+def main():
+    parser = argparse.ArgumentParser(description="LiteScope example on Arty A7")
+    parser.add_argument("--build", action="store_true", help="Build bitstream")
+    parser.add_argument("--load",  action="store_true", help="Load bitstream")
+    args = parser.parse_args()
+
+    soc     = LiteScopeSoC()
+    builder = Builder(soc, csr_csv="csr.csv")
+    builder.build(run=args.build)
+
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
+
+if __name__ == "__main__":
+    main()
diff --git a/litescope/software/litescope_cli.py b/litescope/software/litescope_cli.py
index 8d995b5..2d9ed8f 100755
--- a/litescope/software/litescope_cli.py
+++ b/litescope/software/litescope_cli.py
@@ -28,7 +28,7 @@ class Finder:
         self.signals = signals
 
     def __getitem__(self, name):
-        scores = {s: 0 for s in signals}
+        scores = {s: 0 for s in self.signals}
         # exact match
         if name in scores:
             print("Exact:", name)
@@ -36,7 +36,7 @@ class Finder:
         # substring
         pattern = re.compile(name)
         max_score = 0
-        for s in signals:
+        for s in self.signals:
             match = pattern.search(s)
             if match:
                 scores[s] = match.end() - match.start()