diff --git a/example_designs/targets/simple.py b/example_designs/targets/simple.py
index cf36d9d..f2cc11d 100644
--- a/example_designs/targets/simple.py
+++ b/example_designs/targets/simple.py
@@ -59,6 +59,19 @@ class LiteScopeSoC(SoCCore):
             self.cpu_or_bridge.wishbone
         ]
 
+        # fsm group
+        fsm = FSM(reset_state="STATE1")
+        self.submodules += fsm
+        fsm.act("STATE1",
+            NextState("STATE2")
+        )
+        fsm.act("STATE2",
+            NextState("STATE1")
+        )
+        analyzer_groups[2] = [
+            fsm
+        ]
+
         # analyzer
         self.submodules.analyzer = LiteScopeAnalyzer(analyzer_groups, 512)
 
diff --git a/litescope/core.py b/litescope/core.py
index a2d8c89..ac7b8cb 100644
--- a/litescope/core.py
+++ b/litescope/core.py
@@ -274,6 +274,10 @@ class LiteScopeAnalyzer(Module, AutoCSR):
             for s in signals:
                 if isinstance(s, Record):
                     split_signals.extend(s.flatten())
+                elif isinstance(s, FSM):
+                    s.do_finalize()
+                    s.finalized = True
+                    split_signals.append(s.state)
                 else:
                     split_signals.append(s)
             new_groups[n] = split_signals