diff --git a/example_designs/targets/simple.py b/example_designs/targets/simple.py
index 9bc950c..8e2900b 100644
--- a/example_designs/targets/simple.py
+++ b/example_designs/targets/simple.py
@@ -35,19 +35,10 @@ class LiteScopeSoC(SoCCore):
             except:
                 pass
 
-        self.submodules.counter0 = counter0 = Counter(8)
-        self.submodules.counter1 = counter1 = Counter(8)
-        self.comb += [
-            counter0.ce.eq(1),
-            If(counter0.value == 16,
-                counter0.reset.eq(1),
-                counter1.ce.eq(1)
-            )
-        ]
+        counter = Signal(16)
+        self.sync += counter.eq(counter + 1)
 
-        self.debug = (
-            counter1.value
-        )
+        self.debug = (counter)
         self.submodules.logic_analyzer = LiteScopeLogicAnalyzer(self.debug, 512, with_rle=True, with_subsampler=True)
         self.logic_analyzer.trigger.add_port(LiteScopeTerm(self.logic_analyzer.dw))
 
diff --git a/litescope/common.py b/litescope/common.py
index 890ec44..9241a85 100644
--- a/litescope/common.py
+++ b/litescope/common.py
@@ -1,20 +1,9 @@
 from litex.gen import *
-from litex.gen.genlib.fsm import FSM, NextState
-from litex.gen.fhdl.specials import Memory
 
 from litex.soc.interconnect.csr import *
 from litex.soc.interconnect.stream import *
 
 
-@ResetInserter()
-@CEInserter()
-class Counter(Module):
-    def __init__(self, *args, increment=1, **kwargs):
-        self.value = Signal(*args, **kwargs)
-        self.width = len(self.value)
-        self.sync += self.value.eq(self.value+increment)
-
-
 def data_layout(dw):
     return [("data", dw, DIR_M_TO_S)]
 
diff --git a/litescope/core/storage.py b/litescope/core/storage.py
index de92dc3..ba2f61e 100644
--- a/litescope/core/storage.py
+++ b/litescope/core/storage.py
@@ -9,14 +9,24 @@ class LiteScopeSubSamplerUnit(Module):
 
         # # #
 
-        self.submodules.counter = Counter(32)
+        counter = Signal(32)
+        counter_reset = Signal()
+        counter_ce = Signal()
+        self.sync += \
+            If(counter_reset,
+                counter.eq(0)
+            ).Elif(counter_ce,
+                counter.eq(counter + 1)
+            )
+
+
         done = Signal()
         self.comb += [
-            done.eq(self.counter.value >= self.value),
+            done.eq(self.counter >= self.value),
             Record.connect(sink, source),
             source.stb.eq(sink.stb & done),
-            self.counter.ce.eq(source.ack),
-            self.counter.reset.eq(source.stb & source.ack & done)
+            self.counter_ce.eq(source.ack),
+            self.counter_reset.eq(source.stb & source.ack & done)
         ]
 
 
@@ -45,9 +55,17 @@ class LiteScopeRunLengthEncoderUnit(Module):
         self.submodules.buf = buf = Buffer(sink.description)
         self.comb += Record.connect(sink, buf.d)
 
-        self.submodules.counter = counter = Counter(max=length)
+        counter = Signals(max=length)
+        counter_reset = Signal()
+        counter_ce = Signal()
         counter_done = Signal()
-        self.comb += counter_done.eq(counter.value == length-1)
+        self.sync += \
+            If(counter_reset,
+                counter.eq(0)
+            ).Elif(counter_ce,
+                counter.eq(counter + 1)
+            )
+        self.comb += counter_done.eq(counter == length - 1)
 
         change = Signal()
         self.comb += change.eq(
@@ -58,7 +76,7 @@ class LiteScopeRunLengthEncoderUnit(Module):
         self.submodules.fsm = fsm = FSM(reset_state="BYPASS")
         fsm.act("BYPASS",
             Record.connect(buf.q, source),
-            counter.reset.eq(1),
+            counter_reset.eq(1),
             If(sink.stb & ~change,
                 If(self.enable,
                     NextState("COUNT")
@@ -67,12 +85,12 @@ class LiteScopeRunLengthEncoderUnit(Module):
         )
         fsm.act("COUNT",
             buf.q.ack.eq(1),
-            counter.ce.eq(sink.stb),
+            counter_ce.eq(sink.stb),
             If(~self.enable,
                 NextState("BYPASS")
             ).Elif(change | counter_done,
                 source.stb.eq(1),
-                source.data[:len(counter.value)].eq(counter.value),
+                source.data[:len(counter)].eq(counter),
                 source.data[-1].eq(1),  # Set RLE bit
                 buf.q.ack.eq(source.ack),
                 If(source.ack,
diff --git a/litescope/core/trigger.py b/litescope/core/trigger.py
index 8317ba1..6c2b7a5 100644
--- a/litescope/core/trigger.py
+++ b/litescope/core/trigger.py
@@ -1,7 +1,8 @@
-from litescope.common import *
 from functools import reduce
 from operator import and_
 
+from litescope.common import *
+
 
 class LiteScopeSumUnit(Module, AutoCSR):
     def __init__(self, ports):