From d4c4bb2c0117438168ad8d6ad4b6488f35fe75aa Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 12 Sep 2015 18:19:30 +0200 Subject: [PATCH] example_designs: add core example --- example_designs/make.py | 53 +++++++++++++++++------- example_designs/targets/core.py | 71 +++++++++++++++++++++++++++++++++ test/Makefile | 1 + 3 files changed, 111 insertions(+), 14 deletions(-) create mode 100644 example_designs/targets/core.py diff --git a/example_designs/make.py b/example_designs/make.py index 7fc3537..6fe8ef4 100644 --- a/example_designs/make.py +++ b/example_designs/make.py @@ -68,26 +68,33 @@ if __name__ == "__main__": else: top_class = target_module.default_subtarget - if args.platform is None: - if hasattr(top_class, "default_platform"): - platform_name = top_class.default_platform - else: - raise ValueError("Target has no default platform, specify a platform with -p your_platform") + if hasattr(top_class, "platform"): + platform = top_class.platform + platform_name = top_class.platform.name else: - platform_name = args.platform - platform_module = _import("mibuild.platforms", platform_name) - platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option) - platform = platform_module.Platform(**platform_kwargs) + if args.platform is None: + if hasattr(top_class, "default_platform"): + platform_name = top_class.default_platform + else: + raise ValueError("Target has no default platform, specify a platform with -p your_platform") + else: + platform_name = args.platform + platform_module = _import("mibuild.platforms", platform_name) + platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option) + platform = platform_module.Platform(**platform_kwargs) build_name = top_class.__name__.lower() + "-" + platform_name top_kwargs = dict((k, autotype(v)) for k, v in args.target_option) soc = top_class(platform, **top_kwargs) soc.finalize() - memory_regions = soc.get_memory_regions() - csr_regions = soc.get_csr_regions() + try: + memory_regions = soc.get_memory_regions() + csr_regions = soc.get_csr_regions() + except: + pass # decode actions - action_list = ["clean", "build-csr-csv", "build-bitstream", "load-bitstream", "all"] + action_list = ["clean", "build-csr-csv", "build-core", "build-bitstream", "load-bitstream", "all"] actions = {k: False for k in action_list} for action in args.action: if action in actions: @@ -108,11 +115,17 @@ if __name__ == "__main__": A small footprint and configurable embedded FPGA logic analyzer core powered by Migen -====== Building parameters: ====== +====== Building parameters: ======""") +if hasattr(soc, "io"): + print(""" LiscopeIO --------- Width: {} +""".format(soc.io.dw) +) +if hasattr(soc, "la"): + print(""" LiscopeLA --------- Width: {} @@ -120,7 +133,6 @@ Depth: {} Subsampler: {} RLE: {} ===============================""".format( - soc.io.dw, soc.la.dw, soc.la.depth, str(soc.la.with_subsampler), @@ -144,6 +156,19 @@ RLE: {} csr_csv = cpuif.get_csr_csv(csr_regions) write_to_file(args.csr_csv, csr_csv) + if actions["build-core"]: + ios = soc.get_ios() + if not isinstance(soc, _Fragment): + soc = soc.get_fragment() + platform.finalize(soc) + so = { + NoRetiming: XilinxNoRetiming, + MultiReg: XilinxMultiReg, + AsyncResetSynchronizer: XilinxAsyncResetSynchronizer + } + v_output = verilog.convert(soc, ios, special_overrides=so) + v_output.write("build/litescope.v") + if actions["build-bitstream"]: build_kwargs = dict((k, autotype(v)) for k, v in args.build_option) vns = platform.build(soc, build_name=build_name, **build_kwargs) diff --git a/example_designs/targets/core.py b/example_designs/targets/core.py new file mode 100644 index 0000000..d35a2dc --- /dev/null +++ b/example_designs/targets/core.py @@ -0,0 +1,71 @@ +from migen.genlib.io import CRG +from migen.genlib.resetsync import AsyncResetSynchronizer + +from mibuild.generic_platform import * +from mibuild.xilinx.platform import XilinxPlatform + +from targets import * + +from misoclib.soc import SoC +from litescope.common import * +from litescope.core.port import LiteScopeTerm +from litescope.frontend.io import LiteScopeIO +from litescope.frontend.la import LiteScopeLA + + +_io = [ + ("sys_clk", 0, Pins("X")), + ("sys_rst", 1, Pins("X")), + ("serial", 0, + Subsignal("tx", Pins("X")), + Subsignal("rx", Pins("X")), + ), + ("bus", 0, Pins(" ".join(["X" for i in range(128)]))) +] + +from misoclib.com.uart.bridge import UARTWishboneBridge + +class CorePlatform(XilinxPlatform): + name = "core" + default_clk_name = "sys_clk" + def __init__(self): + XilinxPlatform.__init__(self, "", _io) + + def do_finalize(self, *args, **kwargs): + pass + + +class Core(SoC): + platform = CorePlatform() + csr_map = { + "la": 16 + } + csr_map.update(SoC.csr_map) + + def __init__(self, platform, clk_freq=100*1000000): + self.clk_freq = clk_freq + self.clock_domains.cd_sys = ClockDomain("sys") + SoC.__init__(self, platform, clk_freq, + cpu_type="none", + with_csr=True, csr_data_width=32, + with_uart=False, + with_identifier=True, + with_timer=False + ) + self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)) + self.add_wb_master(self.cpu_or_bridge.wishbone) + + self.bus = platform.request("bus") + self.submodules.la = LiteScopeLA((self.bus), 512, with_rle=True, with_subsampler=True) + self.la.trigger.add_port(LiteScopeTerm(self.la.dw)) + + def get_ios(self): + ios = set() + ios = ios.union({self.cd_sys.clk, + self.cd_sys.rst}) + ios = ios.union({self.platform.lookup_request("serial").rx, + self.platform.lookup_request("serial").tx}) + ios = ios.union({self.bus}) + return ios + +default_subtarget = Core diff --git a/test/Makefile b/test/Makefile index c0ea7a2..3819043 100644 --- a/test/Makefile +++ b/test/Makefile @@ -4,3 +4,4 @@ PYTHON = python3 example_designs: cd ../example_designs && $(PYTHON) make.py -t simple -p de0nano -Ob run False build-bitstream cd ../example_designs && $(PYTHON) make.py -t simple -p kc705 -Ob run False build-bitstream + cd ../example_designs && $(PYTHON) make.py -t core build-core