diff --git a/example_designs/make.py b/example_designs/make.py
old mode 100644
new mode 100755
index eb60eaf..582cd27
--- a/example_designs/make.py
+++ b/example_designs/make.py
@@ -160,12 +160,8 @@ Depth: {}
     if actions["build-core"]:
         soc_fragment = soc.get_fragment()
         platform.finalize(soc_fragment)
-        so = {
-            NoRetiming:             XilinxNoRetimingVivado,
-            MultiReg:               XilinxMultiRegVivado,
-            AsyncResetSynchronizer: XilinxAsyncResetSynchronizer
-        }
-        v_output = platform.get_verilog(soc_fragment, name="litescope", special_overrides=so)
+        v_output = platform.get_verilog(soc_fragment, name="litescope",
+            special_overrides=xilinx_special_overrides)
         v_output.write("build/litescope.v")
 
     if actions["build-bitstream"]: