example_designs: keep up to date with litex
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@ -160,12 +160,8 @@ Depth: {}
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if actions["build-core"]:
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if actions["build-core"]:
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soc_fragment = soc.get_fragment()
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soc_fragment = soc.get_fragment()
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platform.finalize(soc_fragment)
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platform.finalize(soc_fragment)
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so = {
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v_output = platform.get_verilog(soc_fragment, name="litescope",
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NoRetiming: XilinxNoRetimingVivado,
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special_overrides=xilinx_special_overrides)
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MultiReg: XilinxMultiRegVivado,
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AsyncResetSynchronizer: XilinxAsyncResetSynchronizer
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}
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v_output = platform.get_verilog(soc_fragment, name="litescope", special_overrides=so)
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v_output.write("build/litescope.v")
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v_output.write("build/litescope.v")
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if actions["build-bitstream"]:
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if actions["build-bitstream"]:
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