example_designs: keep up to date with litex

This commit is contained in:
Florent Kermarrec 2017-09-25 12:54:25 +02:00
parent d4d63d7474
commit d5887a3eb0
1 changed files with 2 additions and 6 deletions

8
example_designs/make.py Normal file → Executable file
View File

@ -160,12 +160,8 @@ Depth: {}
if actions["build-core"]: if actions["build-core"]:
soc_fragment = soc.get_fragment() soc_fragment = soc.get_fragment()
platform.finalize(soc_fragment) platform.finalize(soc_fragment)
so = { v_output = platform.get_verilog(soc_fragment, name="litescope",
NoRetiming: XilinxNoRetimingVivado, special_overrides=xilinx_special_overrides)
MultiReg: XilinxMultiRegVivado,
AsyncResetSynchronizer: XilinxAsyncResetSynchronizer
}
v_output = platform.get_verilog(soc_fragment, name="litescope", special_overrides=so)
v_output.write("build/litescope.v") v_output.write("build/litescope.v")
if actions["build-bitstream"]: if actions["build-bitstream"]: