From f8e3e63ef3d0b93249b619b90dbf044247aeae09 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sun, 3 Apr 2016 22:54:38 +0200
Subject: [PATCH] fix cd_ratio support

---
 litescope/core.py                     | 20 ++++++++++----------
 litescope/software/driver/analyzer.py |  2 +-
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/litescope/core.py b/litescope/core.py
index 62ef558..0060f41 100644
--- a/litescope/core.py
+++ b/litescope/core.py
@@ -10,8 +10,8 @@ from litex.soc.interconnect import stream
 def ceil_pow2(v):
     return 2**(bits_for(v-1))
 
-def core_layout(dw):
-    return [("data", dw), ("hit", 1)]
+def core_layout(dw, hw=1):
+    return [("data", dw), ("hit", hw)]
 
 class FrontendTrigger(Module, AutoCSR):
     def __init__(self, dw, cd):
@@ -82,10 +82,10 @@ class AnalyzerFrontend(Module, AutoCSR):
         self.submodules.subsampler = FrontendSubSampler(dw, cd)
         self.submodules.converter = ClockDomainsRenamer(cd)(
                                         stream.StrideConverter(
-                                            core_layout(dw),
-                                            core_layout(dw*cd_ratio)))
+                                            core_layout(dw, 1),
+                                            core_layout(dw*cd_ratio, cd_ratio)))
         self.submodules.fifo = ClockDomainsRenamer({"write": cd, "read": "sys"})(
-                                   stream.AsyncFIFO(core_layout(dw*cd_ratio), 8))
+                                   stream.AsyncFIFO(core_layout(dw*cd_ratio, cd_ratio), 8))
 
         self.submodules.pipeline = stream.Pipeline(self.sink,
                                                    self.buffer,
@@ -97,8 +97,8 @@ class AnalyzerFrontend(Module, AutoCSR):
 
 
 class AnalyzerStorage(Module, AutoCSR):
-    def __init__(self, dw, depth):
-        self.sink = stream.Endpoint(core_layout(dw))
+    def __init__(self, dw, depth, cd_ratio):
+        self.sink = stream.Endpoint(core_layout(dw, cd_ratio))
 
         self.start = CSR()
         self.length = CSRStorage(bits_for(depth))
@@ -114,7 +114,7 @@ class AnalyzerStorage(Module, AutoCSR):
 
         # # #
 
-        mem = stream.SyncFIFO([("data", dw)], depth, buffered=True)
+        mem = stream.SyncFIFO([("data", dw)], depth//cd_ratio, buffered=True)
         self.submodules += mem
 
         fsm = FSM(reset_state="IDLE")
@@ -131,7 +131,7 @@ class AnalyzerStorage(Module, AutoCSR):
         fsm.act("WAIT",
             self.wait.status.eq(1),
             self.sink.connect(mem.sink, leave_out=set(["hit"])),
-            If(self.sink.valid & self.sink.hit,
+            If(self.sink.valid & (self.sink.hit != 0),
                 NextState("RUN")
             ),
             mem.source.ready.eq(mem.level >= self.offset.storage)
@@ -176,7 +176,7 @@ class LiteScopeAnalyzer(Module, AutoCSR):
         # # #
 
         self.submodules.frontend = AnalyzerFrontend(self.dw, cd, cd_ratio)
-        self.submodules.storage = AnalyzerStorage(self.core_dw, depth//cd_ratio)
+        self.submodules.storage = AnalyzerStorage(self.core_dw, depth, cd_ratio)
 
         self.comb += [
             self.frontend.sink.valid.eq(1),
diff --git a/litescope/software/driver/analyzer.py b/litescope/software/driver/analyzer.py
index 5842c76..ef4670a 100644
--- a/litescope/software/driver/analyzer.py
+++ b/litescope/software/driver/analyzer.py
@@ -92,7 +92,7 @@ class LiteScopeAnalyzerDriver():
         if self.cd_ratio > 1:
             new_data = DumpData(self.dw)
             for data in self.data:
-                for i in range(self.clk_ratio):
+                for i in range(self.cd_ratio):
                     new_data.append(*get_bits([data], i*self.dw, (i+1)*self.dw))
             self.data = new_data
         return self.data