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fix cd_ratio support

This commit is contained in:
Florent Kermarrec 2016-04-03 22:54:38 +02:00
parent 0c41c6a204
commit f8e3e63ef3
2 changed files with 11 additions and 11 deletions
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20
litescope/core.py
View File

@ -10,8 +10,8 @@ from litex.soc.interconnect import stream
def ceil_pow2(v): def ceil_pow2(v):
return 2**(bits_for(v-1)) return 2**(bits_for(v-1))
def core_layout(dw): def core_layout(dw, hw=1):
return [("data", dw), ("hit", 1)] return [("data", dw), ("hit", hw)]
class FrontendTrigger(Module, AutoCSR): class FrontendTrigger(Module, AutoCSR):
def __init__(self, dw, cd): def __init__(self, dw, cd):
@ -82,10 +82,10 @@ class AnalyzerFrontend(Module, AutoCSR):
self.submodules.subsampler = FrontendSubSampler(dw, cd) self.submodules.subsampler = FrontendSubSampler(dw, cd)
self.submodules.converter = ClockDomainsRenamer(cd)( self.submodules.converter = ClockDomainsRenamer(cd)(
stream.StrideConverter( stream.StrideConverter(
core_layout(dw), core_layout(dw, 1),
core_layout(dw*cd_ratio))) core_layout(dw*cd_ratio, cd_ratio)))
self.submodules.fifo = ClockDomainsRenamer({"write": cd, "read": "sys"})( self.submodules.fifo = ClockDomainsRenamer({"write": cd, "read": "sys"})(
stream.AsyncFIFO(core_layout(dw*cd_ratio), 8)) stream.AsyncFIFO(core_layout(dw*cd_ratio, cd_ratio), 8))
self.submodules.pipeline = stream.Pipeline(self.sink, self.submodules.pipeline = stream.Pipeline(self.sink,
self.buffer, self.buffer,
@ -97,8 +97,8 @@ class AnalyzerFrontend(Module, AutoCSR):
class AnalyzerStorage(Module, AutoCSR): class AnalyzerStorage(Module, AutoCSR):
def __init__(self, dw, depth): def __init__(self, dw, depth, cd_ratio):
self.sink = stream.Endpoint(core_layout(dw)) self.sink = stream.Endpoint(core_layout(dw, cd_ratio))
self.start = CSR() self.start = CSR()
self.length = CSRStorage(bits_for(depth)) self.length = CSRStorage(bits_for(depth))
@ -114,7 +114,7 @@ class AnalyzerStorage(Module, AutoCSR):
# # # # # #
mem = stream.SyncFIFO([("data", dw)], depth, buffered=True) mem = stream.SyncFIFO([("data", dw)], depth//cd_ratio, buffered=True)
self.submodules += mem self.submodules += mem
fsm = FSM(reset_state="IDLE") fsm = FSM(reset_state="IDLE")
@ -131,7 +131,7 @@ class AnalyzerStorage(Module, AutoCSR):
fsm.act("WAIT", fsm.act("WAIT",
self.wait.status.eq(1), self.wait.status.eq(1),
self.sink.connect(mem.sink, leave_out=set(["hit"])), self.sink.connect(mem.sink, leave_out=set(["hit"])),
If(self.sink.valid & self.sink.hit, If(self.sink.valid & (self.sink.hit != 0),
NextState("RUN") NextState("RUN")
), ),
mem.source.ready.eq(mem.level >= self.offset.storage) mem.source.ready.eq(mem.level >= self.offset.storage)
@ -176,7 +176,7 @@ class LiteScopeAnalyzer(Module, AutoCSR):
# # # # # #
self.submodules.frontend = AnalyzerFrontend(self.dw, cd, cd_ratio) self.submodules.frontend = AnalyzerFrontend(self.dw, cd, cd_ratio)
self.submodules.storage = AnalyzerStorage(self.core_dw, depth//cd_ratio) self.submodules.storage = AnalyzerStorage(self.core_dw, depth, cd_ratio)
self.comb += [ self.comb += [
self.frontend.sink.valid.eq(1), self.frontend.sink.valid.eq(1),

2
litescope/software/driver/analyzer.py
View File

@ -92,7 +92,7 @@ class LiteScopeAnalyzerDriver():
if self.cd_ratio > 1: if self.cd_ratio > 1:
new_data = DumpData(self.dw) new_data = DumpData(self.dw)
for data in self.data: for data in self.data:
for i in range(self.clk_ratio): for i in range(self.cd_ratio):
new_data.append(*get_bits([data], i*self.dw, (i+1)*self.dw)) new_data.append(*get_bits([data], i*self.dw, (i+1)*self.dw))
self.data = new_data self.data = new_data
return self.data return self.data