f7a9672284
platforms/targets: switch to LiteX-Boards.
2021-01-04 14:14:45 +01:00
f78400aa29
ci: install RISC-V GCC.
2020-12-17 16:56:31 +01:00
c8b7e1a922
litescope/core: set default csr_csv to csr_csv="analyzer.csv".
...
Simplify creating basic analyzer:
from litescope import LiteScopeAnalyzer
analyzer_signals = [...]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, depth=512)
self.add_csr("analyzer")
2020-11-30 15:04:09 +01:00
0a67448ce9
ci: migrate from Travis CI to Github Actions.
2020-11-24 13:55:54 +01:00
94e2d15c94
software/litescope_cli: cleanup, use --csv to select analyzer file and add --dump argument.
2020-10-30 11:58:38 +01:00
e6e5675100
software/litescope_cli: add name support (default="analyzer").
...
We can have several analyzers in the design, this allows selecting the one to use.
2020-10-23 10:31:46 +02:00
d6911390c0
software/litescope_cli: add group support.
2020-10-16 10:40:24 +02:00
dc9109030a
software/driver/analyzer/add_trigger: add support for binary/hexa expressions with x support.
...
ex: litescope_cli -v sig1 0b111x0
ex: litescope_cli -v sig2 0x1234567x
2020-09-03 13:16:32 +02:00
69de7c4930
software/Dump: add add_scope_clk and add_scope_trig methods and add scope_clk/trig to dumps.
2020-09-03 09:23:19 +02:00
219a90122f
core/Trigger: also apply mask to trigger value (avoid having doing it in software).
2020-09-02 17:09:25 +02:00
12be70325e
software/litescope_cli: set default length to None (do a capture with max depth).
2020-09-02 10:55:32 +02:00
bd10138124
core/_Storage: fix size of length/offset signals.
2020-09-02 10:54:38 +02:00
02b543e5ba
litescope_cli: add capture subsampling support.
2020-08-25 09:28:15 +02:00
2739d5a069
add SPDX License identifier to header and specify file is part of LiteScope.
2020-08-23 16:45:20 +02:00
ec7bd6b47d
getting started: update.
2020-08-07 23:10:29 +02:00
7d227740bd
Merge pull request #27 from cklarhorst/fix-storage-wrong-clock-domain
...
Fix: 2 signals in the storage class belong to the wrong clock domain
2020-08-07 14:20:14 +02:00
ad4e46c8c6
Fix: 2 signals in the storage class belong to the wrong clock domain
...
Signals & Domain overview:
- self.{offset,length}.storage belong to sys clock
- offset, length belong to scope clock
- mem belongs to scope clock
Therefore, everything that involves mem needs to use offset/length
2020-08-07 13:56:06 +02:00
2ad73a0f54
Merge pull request #25 from cklarhorst/fix-trigger-flush-timer-wrong-clock-domain
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Fix: A WaitTimer belongs to the wrong clock domain (trigger flush)
2020-08-05 23:10:26 +02:00
16e65556a2
Fix: A WaitTimer belongs to the wrong clock domain (trigger flush)
...
The WaitTimer for the trigger flush should belong to the scope clock
instead of the sys clock
2020-08-05 16:21:08 +02:00
0066866000
travis: install riscv toolchain for example.
2020-08-05 15:51:01 +02:00
6a322ed405
test/test_examples: update.
2020-08-05 14:51:50 +02:00
bc6c5e35ee
examples: add mininal example on Arty with Etherbone and ibus/counter on analyzer.
2020-08-05 13:22:29 +02:00
0182377a07
examples: remove obsolete examples rename litescope_test to litescope_cli and add it as console script.
2020-08-05 12:41:50 +02:00
a80c964075
Merge pull request #22 from antmicro/jboc/test-script
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Add a script for testing LiteScope
2020-07-28 11:25:28 +02:00
8b0274d2eb
examples: add a more general script for testing
2020-07-24 12:39:11 +02:00
15179cb46f
examples/targets/simple: update.
2020-06-26 19:14:50 +02:00
0e1ca9ee31
examples/make: update.
2020-06-17 21:22:17 +02:00
54488c0f4d
README: switch to markdown.
2020-04-11 19:52:08 +02:00
72277ffd9b
examples: use CRG from litex.build.
2020-04-10 10:29:35 +02:00
a05312d4e2
litex.build: update from migen.genlib.io litex.build.io.
2020-04-10 09:22:40 +02:00
5701c526fd
.travis.yml: fix git clone error.
2020-04-07 12:20:26 +02:00
47819e803b
setup.py: simplify, switch to Python3.6+ (using python_requires), remove version.
...
- Deprecate Python 3.5, switch to Python 3.6+.
- Remove which was not used or updated. We'll see to get this back when working on releases.
2020-04-07 11:58:21 +02:00
b3d1e6938f
Merge pull request #16 from zyp/sigrok_width
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software/dump/sigrok: Support width > 1.
2020-02-26 22:12:14 +01:00
9dd2e968e9
examples: simplify/update
2020-02-26 22:03:00 +01:00
e07bdbfb29
software/dump/sigrok: Support width > 1.
2020-02-26 18:23:45 +01:00
daf10e9473
examples/make: based on Migen & LiteX
2019-12-02 13:03:02 +01:00
a255bc28ed
test: replace Makefile with test_examples, also integrate fast_scope_arty example
2019-11-23 11:16:32 +01:00
63c15167e1
example/fast_scope_arty: cleanup imports, remove program, allow disabling compilation by passing "no-compile"
2019-11-23 11:15:56 +01:00
bcd883ef8e
README: update
2019-11-22 19:47:46 +01:00
1f09678653
core: remove cd parameter retro-compatibility
2019-11-22 19:42:52 +01:00
c1b52f1887
core: cosmetic
2019-11-22 19:42:04 +01:00
c85c25bb78
add Travis-CI
2019-11-22 19:37:06 +01:00
5e7ee3555b
LICENSE/setup: update
2019-11-22 19:36:44 +01:00
6430dd09d0
test: update and add auto-check
2019-11-22 19:36:26 +01:00
bbc98b4404
core: remove reset on scope clk
2019-11-22 19:34:07 +01:00
1448b55819
examples: keep up to date with LiteX
2019-11-08 12:39:34 +01:00
7a9fa9d3b1
core: use new CSRStatus.we signal to speed-up Storage upload (>10x speedup over ethernet)
2019-09-24 18:03:06 +02:00
284253d558
core: add csr_csv parameter and export csv_csv on do_exit
2019-09-10 12:38:34 +02:00
69a8df013d
Merge pull request #14 from DurandA/master
...
Use cpu instead of cpu_or_bridge in examples
2019-08-20 14:40:01 +02:00
06cac3a142
Use cpu instead of cpu_or_bridge in examples
2019-08-20 13:55:00 +02:00
Florent Kermarrec
Christian Klarhorst
Jędrzej Boczar
Vegard Storheil Eriksen
Arnaud Durand