108 lines
3.9 KiB
Markdown
108 lines
3.9 KiB
Markdown
```
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__ _ __ ____
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/ / (_) /____ / __/______ ___ ___
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/ /__/ / __/ -_)\ \/ __/ _ \/ _ \/ -_)
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/____/_/\__/\__/___/\__/\___/ .__/\__/
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/_/
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Copyright 2015-2020 / EnjoyDigital
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A small footprint and configurable Logic Analyzer
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core powered by Migen & LiteX
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```
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[](https://github.com/enjoy-digital/litescope/actions) 
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[> Intro
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--------
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LiteScope provides a small footprint and configurable embedded logic analyzer that you
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can use in your FPGA and aims to provide a free, portable and flexible
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alternative to vendor's solutions!
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LiteScope is part of LiteX libraries whose aims are to lower entry level of
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complex FPGA cores by providing simple, elegant and efficient implementations
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of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
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Using Migen to describe the HDL allows the core to be highly and easily configurable.
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LiteScope can be used as LiteX library or can be integrated with your standard
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design flow by generating the verilog rtl that you will use as a standard core.
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[> Features
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-----------
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- IO peek and poke with LiteScopeIO.
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- Logic analyser with LiteScopeAnalyzer:
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- Subsampling.
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- Data storage in Block RAM.
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- Configurable triggers.
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- Bridges:
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- UART <--> Wishbone (provided by LiteX)
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- Ethernet <--> Wishbone ("Etherbone") (provided by LiteEth)
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- PCIe <--> Wishbone (provided by LitePCIe)
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- Exports formats: .vcd, .sr(sigrok), .csv, .py, etc...
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[> Proven
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---------
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LiteScope has already been used to investigate issues on several commercial or
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open-source designs.
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[> Possible improvements
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------------------------
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- add standardized interfaces (AXI, Avalon-ST)
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- add protocols analyzers
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- add signals injection/generation
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- add storage in DRAM
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- add storage in HDD with LiteSATA core
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- ... See below Support and consulting :)
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If you want to support these features, please contact us at florent [AT]
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enjoy-digital.fr.
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[> Getting started
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------------------
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1. Install Python 3.6+ and FPGA vendor's development tools.
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2. Install LiteX and the cores by following the LiteX's wiki [installation guide](https://github.com/enjoy-digital/litex/wiki/Installation).
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3. You can find examples of integration of the core with LiteX in LiteX-Boards and in the examples directory.
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[> Tests
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--------
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Unit tests are available in ./test/.
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To run all the unit tests:
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```sh
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$ ./setup.py test
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```
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Tests can also be run individually:
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```sh
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$ python3 -m unittest test.test_name
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```
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[> License
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----------
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LiteScope is released under the very permissive two-clause BSD license. Under
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the terms of this license, you are authorized to use LiteScope for closed-source
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proprietary designs.
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Even though we do not require you to do so, those things are awesome, so please
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do them if possible:
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- tell us that you are using LiteScope
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- cite LiteScope in publications related to research it has helped
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- send us feedback and suggestions for improvements
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- send us bug reports when something goes wrong
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- send us the modifications and improvements you have done to LiteScope.
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[> Support and consulting
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-------------------------
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We love open-source hardware and like sharing our designs with others.
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LiteScope is developed and maintained by EnjoyDigital.
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If you would like to know more about LiteScope or if you are already a happy
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user and would like to extend it for your needs, EnjoyDigital can provide standard
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commercial support as well as consulting services.
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So feel free to contact us, we'd love to work with you! (and eventually shorten
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the list of the possible improvements :)
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[> Contact
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----------
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E-mail: florent [AT] enjoy-digital.fr |