52 lines
1.7 KiB
Python
52 lines
1.7 KiB
Python
#
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# This file is part of LiteScope.
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#
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# Copyright (c) 2017-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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from migen import *
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from litescope import LiteScopeAnalyzer
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class TestAnalyzer(unittest.TestCase):
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def test_analyzer(self):
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def generator(dut):
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dut.data = []
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# Configure Trigger
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yield from dut.analyzer.trigger.mem_value.write(0x0010)
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yield from dut.analyzer.trigger.mem_mask.write(0xffff)
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yield from dut.analyzer.trigger.mem_write.write(1)
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# Configure Subsampler
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yield from dut.analyzer.subsampler.value.write(2)
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# Configure Storage
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yield from dut.analyzer.storage.length.write(256)
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yield from dut.analyzer.storage.offset.write(8)
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yield from dut.analyzer.storage.enable.write(1)
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yield
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for i in range(16):
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yield
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# Wait capture
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while not (yield from dut.analyzer.storage.done.read()):
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yield
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# Reade captured datas
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while (yield from dut.analyzer.storage.mem_valid.read()):
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dut.data.append((yield from dut.analyzer.storage.mem_data.read()))
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yield
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class DUT(Module):
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def __init__(self):
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counter = Signal(16)
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self.sync += counter.eq(counter + 1)
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self.submodules.analyzer = LiteScopeAnalyzer(counter, 512)
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dut = DUT()
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generators = {"sys" : [generator(dut)]}
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clocks = {"sys": 10, "scope": 10}
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run_simulation(dut, generators, clocks)
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self.assertEqual(dut.data, [524 + 3*i for i in range(256)])
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