diff --git a/litex_boards/platforms/efinix_trion_t20_bga256_dev_kit.py b/litex_boards/platforms/efinix_trion_t20_bga256_dev_kit.py index a06fe82..512345e 100644 --- a/litex_boards/platforms/efinix_trion_t20_bga256_dev_kit.py +++ b/litex_boards/platforms/efinix_trion_t20_bga256_dev_kit.py @@ -2,8 +2,6 @@ # This file is part of LiteX-Boards. # # Copyright (c) 2021 Miodrag Milanovic -# Copyright (c) 2021 Franck Jullien -# Copyright (c) 2021 Florent Kermarrec # SPDX-License-Identifier: BSD-2-Clause from litex.build.generic_platform import * @@ -16,6 +14,13 @@ _io = [ # Clk ("clk50", 0, Pins("L13"), IOStandard("3.3_V_LVTTL_/_LVCMOS")), + # Serial + ("serial", 0, + Subsignal("tx", Pins("H4:18")), # 27 on H4 + Subsignal("rx", Pins("H4:19")), # 28 on H4 + IOStandard("3.3_V_LVTTL_/_LVCMOS") , Misc("WEAK_PULLUP") + ), + # Leds ("user_led", 0, Pins("D14"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")), ("user_led", 1, Pins("E13"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")), diff --git a/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py b/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py index 2a70d94..2ae5ddb 100755 --- a/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py +++ b/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py @@ -39,21 +39,11 @@ class _CRG(Module): pll.register_clkin(clk50, 50e6) pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True) -# Default peripherals -serial = [ - ("serial", 0, - Subsignal("tx", Pins("H4:18")), # 27 on H4 - Subsignal("rx", Pins("H4:19")), # 28 on H4 - IOStandard("3.3_V_LVTTL_/_LVCMOS") , Misc("WEAK_PULLUP") - ) -] - # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(100e6), with_spi_flash=False, with_led_chaser=True, **kwargs): platform = efinix_trion_t20_bga256_dev_kit.Platform() - platform.add_extension(serial) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq,