From 028d4a78aa8f6750f7be0880f373ce88495592ab Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 13 Jan 2020 15:20:37 +0100 Subject: [PATCH] targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args --- litex_boards/community/targets/ac701.py | 5 +---- litex_boards/community/targets/de10lite.py | 4 +--- litex_boards/community/targets/de1soc.py | 4 +--- litex_boards/community/targets/de2_115.py | 5 +---- litex_boards/community/targets/ecp5_evn.py | 4 +--- litex_boards/community/targets/pipistrello.py | 7 ++----- litex_boards/official/targets/arty.py | 9 +++------ litex_boards/official/targets/de0nano.py | 4 +--- litex_boards/official/targets/genesys2.py | 9 +++------ litex_boards/official/targets/kc705.py | 9 +++------ litex_boards/official/targets/kcu105.py | 9 +++------ litex_boards/official/targets/minispartan6.py | 4 +--- litex_boards/official/targets/nexys4ddr.py | 9 +++------ litex_boards/official/targets/nexys_video.py | 9 +++------ litex_boards/official/targets/simple.py | 9 +++------ litex_boards/official/targets/versa_ecp5.py | 8 +++----- litex_boards/partner/targets/aller.py | 2 -- litex_boards/partner/targets/c10lprefkit.py | 4 +--- litex_boards/partner/targets/camlink_4k.py | 4 +--- litex_boards/partner/targets/hadbadge.py | 4 +--- litex_boards/partner/targets/nereid.py | 2 -- litex_boards/partner/targets/netv2.py | 9 +++------ litex_boards/partner/targets/orangecrab.py | 6 ++---- litex_boards/partner/targets/tagus.py | 2 -- litex_boards/partner/targets/trellisboard.py | 8 +++----- litex_boards/partner/targets/ulx3s.py | 4 +--- 26 files changed, 45 insertions(+), 108 deletions(-) diff --git a/litex_boards/community/targets/ac701.py b/litex_boards/community/targets/ac701.py index f9d7752..ad9490a 100755 --- a/litex_boards/community/targets/ac701.py +++ b/litex_boards/community/targets/ac701.py @@ -51,10 +51,7 @@ class BaseSoC(SoCSDRAM): platform = ac701.Platform() # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=0x8000, - integrated_sram_size=0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/community/targets/de10lite.py b/litex_boards/community/targets/de10lite.py index aa02e45..e14b23f 100755 --- a/litex_boards/community/targets/de10lite.py +++ b/litex_boards/community/targets/de10lite.py @@ -85,9 +85,7 @@ class BaseSoC(SoCSDRAM): platform = de10lite.Platform() # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform) diff --git a/litex_boards/community/targets/de1soc.py b/litex_boards/community/targets/de1soc.py index 410c21b..15c466f 100755 --- a/litex_boards/community/targets/de1soc.py +++ b/litex_boards/community/targets/de1soc.py @@ -76,9 +76,7 @@ class BaseSoC(SoCSDRAM): platform = de1soc.Platform() # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform) diff --git a/litex_boards/community/targets/de2_115.py b/litex_boards/community/targets/de2_115.py index 11d5672..3623534 100755 --- a/litex_boards/community/targets/de2_115.py +++ b/litex_boards/community/targets/de2_115.py @@ -76,9 +76,7 @@ class BaseSoC(SoCSDRAM): platform = de2_115.Platform() # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform) @@ -86,7 +84,6 @@ class BaseSoC(SoCSDRAM): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) - # ISSI IS42S16320D-7TL sdram_module = IS42S16320(self.clk_freq, "1:1") self.register_sdram(self.sdrphy, geom_settings = sdram_module.geom_settings, diff --git a/litex_boards/community/targets/ecp5_evn.py b/litex_boards/community/targets/ecp5_evn.py index fc1f5af..bc2b6d5 100755 --- a/litex_boards/community/targets/ecp5_evn.py +++ b/litex_boards/community/targets/ecp5_evn.py @@ -45,9 +45,7 @@ class BaseSoC(SoCCore): platform = ecp5_evn.Platform(toolchain=toolchain) # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=0x8000, - **kwargs) + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- crg = _CRG(platform, sys_clk_freq, x5_clk_freq) diff --git a/litex_boards/community/targets/pipistrello.py b/litex_boards/community/targets/pipistrello.py index 45466a1..c6ce8c8 100755 --- a/litex_boards/community/targets/pipistrello.py +++ b/litex_boards/community/targets/pipistrello.py @@ -147,15 +147,12 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, integrated_rom_size=0x8000, **kwargs): + def __init__(self, **kwargs): sys_clk_freq = (83 + Fraction(1, 3))*1000*1000 platform = pipistrello.Platform() # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=integrated_rom_size, - integrated_sram_size=0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/official/targets/arty.py b/litex_boards/official/targets/arty.py index 1593db3..1e774e3 100755 --- a/litex_boards/official/targets/arty.py +++ b/litex_boards/official/targets/arty.py @@ -48,14 +48,11 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs): + def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = arty.Platform() # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=integrated_rom_size, - integrated_sram_size=0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -81,7 +78,7 @@ class EthernetSoC(BaseSoC): mem_map.update(BaseSoC.mem_map) def __init__(self, **kwargs): - BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs) + BaseSoC.__init__(self, **kwargs) self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks"), self.platform.request("eth")) diff --git a/litex_boards/official/targets/de0nano.py b/litex_boards/official/targets/de0nano.py index 553a2f2..b9385f2 100755 --- a/litex_boards/official/targets/de0nano.py +++ b/litex_boards/official/targets/de0nano.py @@ -76,9 +76,7 @@ class BaseSoC(SoCSDRAM): platform = de0nano.Platform() # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform) diff --git a/litex_boards/official/targets/genesys2.py b/litex_boards/official/targets/genesys2.py index ecad089..b3c596c 100755 --- a/litex_boards/official/targets/genesys2.py +++ b/litex_boards/official/targets/genesys2.py @@ -41,14 +41,11 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(125e6), integrated_rom_size=0x8000, **kwargs): + def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = genesys2.Platform() # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size = integrated_rom_size, - integrated_sram_size = 0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -72,7 +69,7 @@ class EthernetSoC(BaseSoC): mem_map.update(BaseSoC.mem_map) def __init__(self, **kwargs): - BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs) + BaseSoC.__init__(self, **kwargs) self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"), self.platform.request("eth")) diff --git a/litex_boards/official/targets/kc705.py b/litex_boards/official/targets/kc705.py index 8746080..0cbf789 100755 --- a/litex_boards/official/targets/kc705.py +++ b/litex_boards/official/targets/kc705.py @@ -43,14 +43,11 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(125e6), integrated_rom_size=0x8000, **kwargs): + def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = kc705.Platform() # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size = integrated_rom_size, - integrated_sram_size = 0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -76,7 +73,7 @@ class EthernetSoC(BaseSoC): mem_map.update(BaseSoC.mem_map) def __init__(self, **kwargs): - BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs) + BaseSoC.__init__(self, **kwargs) self.submodules.ethphy = LiteEthPHY(self.platform.request("eth_clocks"), self.platform.request("eth"), clk_freq=self.clk_freq) diff --git a/litex_boards/official/targets/kcu105.py b/litex_boards/official/targets/kcu105.py index ec36e9d..2accee5 100755 --- a/litex_boards/official/targets/kcu105.py +++ b/litex_boards/official/targets/kcu105.py @@ -77,14 +77,11 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(125e6), integrated_rom_size=0x8000, **kwargs): + def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = kcu105.Platform() # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size = integrated_rom_size, - integrated_sram_size = 0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -111,7 +108,7 @@ class EthernetSoC(BaseSoC): mem_map.update(BaseSoC.mem_map) def __init__(self, **kwargs): - BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs) + BaseSoC.__init__(self, **kwargs) self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1) self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk, diff --git a/litex_boards/official/targets/minispartan6.py b/litex_boards/official/targets/minispartan6.py index 917baee..6a74092 100755 --- a/litex_boards/official/targets/minispartan6.py +++ b/litex_boards/official/targets/minispartan6.py @@ -49,9 +49,7 @@ class BaseSoC(SoCSDRAM): platform = minispartan6.Platform() # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size = 0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/official/targets/nexys4ddr.py b/litex_boards/official/targets/nexys4ddr.py index fa5c164..6ce90cb 100755 --- a/litex_boards/official/targets/nexys4ddr.py +++ b/litex_boards/official/targets/nexys4ddr.py @@ -45,14 +45,11 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs): + def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = nexys4ddr.Platform() # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size = integrated_rom_size, - integrated_sram_size = 0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -78,7 +75,7 @@ class EthernetSoC(BaseSoC): mem_map.update(BaseSoC.mem_map) def __init__(self, **kwargs): - BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs) + BaseSoC.__init__(self, **kwargs) self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"), self.platform.request("eth")) diff --git a/litex_boards/official/targets/nexys_video.py b/litex_boards/official/targets/nexys_video.py index efbc0d7..bce71af 100755 --- a/litex_boards/official/targets/nexys_video.py +++ b/litex_boards/official/targets/nexys_video.py @@ -45,14 +45,11 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs): + def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = nexys_video.Platform() # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size = integrated_rom_size, - integrated_sram_size = 0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -78,7 +75,7 @@ class EthernetSoC(BaseSoC): mem_map.update(BaseSoC.mem_map) def __init__(self, **kwargs): - BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs) + BaseSoC.__init__(self, **kwargs) self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"), self.platform.request("eth")) diff --git a/litex_boards/official/targets/simple.py b/litex_boards/official/targets/simple.py index 877719e..0dc5df1 100755 --- a/litex_boards/official/targets/simple.py +++ b/litex_boards/official/targets/simple.py @@ -19,14 +19,11 @@ from liteeth.mac import LiteEthMAC # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, platform, integrated_rom_size=0x8000, **kwargs): + def __init__(self, platform, **kwargs): sys_clk_freq = int(1e9/platform.default_clk_period) # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=integrated_rom_size, - integrated_main_ram_size=16*1024, - **kwargs) + SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request(platform.default_clk_name)) @@ -38,7 +35,7 @@ class EthernetSoC(BaseSoC): } mem_map.update(BaseSoC.mem_map) - def __init__(self, platform, integrated_rom_size=0x10000, **kwargs): + def __init__(self, platform, **kwargs): BaseSoC.__init__(self, platform, **kwargs) self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), diff --git a/litex_boards/official/targets/versa_ecp5.py b/litex_boards/official/targets/versa_ecp5.py index 76e1ca8..41bedb8 100755 --- a/litex_boards/official/targets/versa_ecp5.py +++ b/litex_boards/official/targets/versa_ecp5.py @@ -72,13 +72,11 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", integrated_rom_size=0x8000, **kwargs): + def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs): platform = versa_ecp5.Platform(toolchain=toolchain) # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=integrated_rom_size, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -105,7 +103,7 @@ class EthernetSoC(BaseSoC): mem_map.update(BaseSoC.mem_map) def __init__(self, toolchain="diamond", **kwargs): - BaseSoC.__init__(self, toolchain=toolchain, integrated_rom_size=0x10000, **kwargs) + BaseSoC.__init__(self, toolchain=toolchain, **kwargs) self.submodules.ethphy = LiteEthPHYRGMII( self.platform.request("eth_clocks"), diff --git a/litex_boards/partner/targets/aller.py b/litex_boards/partner/targets/aller.py index 1504a4e..23aec6c 100755 --- a/litex_boards/partner/targets/aller.py +++ b/litex_boards/partner/targets/aller.py @@ -59,8 +59,6 @@ class AllerSoC(SoCSDRAM): # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, sys_clk_freq, csr_data_width = 32, - integrated_rom_size = 0x10000, - integrated_sram_size = 0x10000, integrated_main_ram_size = 0x10000, # FIXME: keep this for initial PCIe tests ident = "Aller LiteX Test SoC", ident_version=True, with_uart=not with_pcie_uart) diff --git a/litex_boards/partner/targets/c10lprefkit.py b/litex_boards/partner/targets/c10lprefkit.py index 4ebd342..7965c67 100755 --- a/litex_boards/partner/targets/c10lprefkit.py +++ b/litex_boards/partner/targets/c10lprefkit.py @@ -94,9 +94,7 @@ class BaseSoC(SoCSDRAM): platform = c10lprefkit.Platform() # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform) diff --git a/litex_boards/partner/targets/camlink_4k.py b/litex_boards/partner/targets/camlink_4k.py index 5ef93ca..b1b8e31 100755 --- a/litex_boards/partner/targets/camlink_4k.py +++ b/litex_boards/partner/targets/camlink_4k.py @@ -71,9 +71,7 @@ class BaseSoC(SoCSDRAM): sys_clk_freq = int(81e6) # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/partner/targets/hadbadge.py b/litex_boards/partner/targets/hadbadge.py index 46bc8a1..58f51c7 100755 --- a/litex_boards/partner/targets/hadbadge.py +++ b/litex_boards/partner/targets/hadbadge.py @@ -52,9 +52,7 @@ class BaseSoC(SoCSDRAM): platform = hadbadge.Platform(toolchain=toolchain) # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/partner/targets/nereid.py b/litex_boards/partner/targets/nereid.py index 11b5588..8a9265c 100755 --- a/litex_boards/partner/targets/nereid.py +++ b/litex_boards/partner/targets/nereid.py @@ -59,8 +59,6 @@ class NereidSoC(SoCSDRAM): # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, sys_clk_freq, csr_data_width = 32, - integrated_rom_size = 0x10000, - integrated_sram_size = 0x10000, integrated_main_ram_size = 0x10000, # FIXME: keep this for initial PCIe tests ident = "Nereid LiteX Test SoC", ident_version=True, with_uart = not with_pcie_uart) diff --git a/litex_boards/partner/targets/netv2.py b/litex_boards/partner/targets/netv2.py index 41e9a7b..8f7e451 100755 --- a/litex_boards/partner/targets/netv2.py +++ b/litex_boards/partner/targets/netv2.py @@ -50,14 +50,11 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs): + def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = netv2.Platform() # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size = integrated_rom_size, - integrated_sram_size = 0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -83,7 +80,7 @@ class EthernetSoC(BaseSoC): mem_map.update(BaseSoC.mem_map) def __init__(self, **kwargs): - BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs) + BaseSoC.__init__(self, **kwargs) self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"), self.platform.request("eth")) diff --git a/litex_boards/partner/targets/orangecrab.py b/litex_boards/partner/targets/orangecrab.py index 9d4b4ed..4d0d914 100755 --- a/litex_boards/partner/targets/orangecrab.py +++ b/litex_boards/partner/targets/orangecrab.py @@ -75,13 +75,11 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(48e6), toolchain="diamond", integrated_rom_size=0x8000, **kwargs): + def __init__(self, sys_clk_freq=int(48e6), toolchain="diamond", **kwargs): platform = orangecrab.Platform(toolchain=toolchain) # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=integrated_rom_size, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/partner/targets/tagus.py b/litex_boards/partner/targets/tagus.py index 38eb92a..0111fd6 100755 --- a/litex_boards/partner/targets/tagus.py +++ b/litex_boards/partner/targets/tagus.py @@ -61,8 +61,6 @@ class TagusSoC(SoCSDRAM): # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, sys_clk_freq, csr_data_width = 32, - integrated_rom_size = 0x10000, - integrated_sram_size = 0x10000, integrated_main_ram_size = 0x10000, # FIXME: keep this for initial PCIe tests ident = "Tagus LiteX Test SoC", ident_version=True, with_uart = not with_pcie_uart) diff --git a/litex_boards/partner/targets/trellisboard.py b/litex_boards/partner/targets/trellisboard.py index 6b75ca9..80b79b0 100755 --- a/litex_boards/partner/targets/trellisboard.py +++ b/litex_boards/partner/targets/trellisboard.py @@ -79,13 +79,11 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", integrated_rom_size=0x8000, **kwargs): + def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs): platform = trellisboard.Platform(toolchain=toolchain) # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=integrated_rom_size, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) @@ -111,7 +109,7 @@ class EthernetSoC(BaseSoC): mem_map.update(BaseSoC.mem_map) def __init__(self, toolchain="diamond", **kwargs): - BaseSoC.__init__(self, toolchain=toolchain, integrated_rom_size=0x10000, **kwargs) + BaseSoC.__init__(self, toolchain=toolchain, **kwargs) self.submodules.ethphy = LiteEthPHYRGMII( self.platform.request("eth_clocks"), diff --git a/litex_boards/partner/targets/ulx3s.py b/litex_boards/partner/targets/ulx3s.py index 39aa3e1..5ba068f 100755 --- a/litex_boards/partner/targets/ulx3s.py +++ b/litex_boards/partner/targets/ulx3s.py @@ -55,9 +55,7 @@ class BaseSoC(SoCSDRAM): platform = ulx3s.Platform(device=device, toolchain=toolchain) # SoCSDRAM --------------------------------------------------------------------------------- - SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, - integrated_rom_size=0x8000, - **kwargs) + SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq)