diff --git a/litex_boards/targets/ecpix5.py b/litex_boards/targets/ecpix5.py
index 5d2cd8f..6a2a7e7 100755
--- a/litex_boards/targets/ecpix5.py
+++ b/litex_boards/targets/ecpix5.py
@@ -111,7 +111,8 @@ class BaseSoC(SoCCore):
         if with_ethernet:
             self.submodules.ethphy = LiteEthPHYRGMII(
                 clock_pads = self.platform.request("eth_clocks"),
-                pads       = self.platform.request("eth"))
+                pads       = self.platform.request("eth"),
+                rx_delay   = 0e-9)
             self.add_csr("ethphy")
             self.add_ethernet(phy=self.ethphy)