diff --git a/litex_boards/targets/xcu1525.py b/litex_boards/targets/xcu1525.py
index 7431a58..6f89966 100755
--- a/litex_boards/targets/xcu1525.py
+++ b/litex_boards/targets/xcu1525.py
@@ -31,7 +31,7 @@ from litepcie.software import generate_litepcie_software
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(Module):
-    def __init__(self, platform, sys_clk_freq):
+    def __init__(self, platform, sys_clk_freq, ddram_channel):
         self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys4x  = ClockDomain(reset_less=True)
         self.clock_domains.cd_pll4x  = ClockDomain(reset_less=True)
@@ -40,7 +40,7 @@ class _CRG(Module):
         # # #
 
         self.submodules.pll = pll = USPMMCM(speedgrade=-2)
-        pll.register_clkin(platform.request("clk300"), 300e6)
+        pll.register_clkin(platform.request("clk300", ddram_channel), 300e6)
         pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
         pll.create_clkout(self.cd_clk500, 500e6, with_reset=False)