From b41d72e1d052aed7212ae5d93bc961e1d51c38c8 Mon Sep 17 00:00:00 2001 From: Hans Baier Date: Sat, 16 Apr 2022 06:36:24 +0700 Subject: [PATCH 1/2] add board support for QMTech EP4CGX150 --- litex_boards/platforms/qmtech_ep4cgx150.py | 158 ++++++++++++++++++ litex_boards/targets/qmtech_ep4cgx150.py | 177 +++++++++++++++++++++ 2 files changed, 335 insertions(+) create mode 100644 litex_boards/platforms/qmtech_ep4cgx150.py create mode 100755 litex_boards/targets/qmtech_ep4cgx150.py diff --git a/litex_boards/platforms/qmtech_ep4cgx150.py b/litex_boards/platforms/qmtech_ep4cgx150.py new file mode 100644 index 0000000..bc87a17 --- /dev/null +++ b/litex_boards/platforms/qmtech_ep4cgx150.py @@ -0,0 +1,158 @@ +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2020 Basel Sayeh +# Copyright (c) 2021 Hans Baier +# SPDX-License-Identifier: BSD-2-Clause + +from litex.build.generic_platform import * +from litex.build.altera import AlteraPlatform +from litex.build.altera.programmer import USBBlaster + +# IOs ---------------------------------------------------------------------------------------------- + +_io = [ + # Clk + ("clk50", 0, Pins("B14"), IOStandard("3.3-V LVTTL")), + + # Button + ("key", 0, Pins("AD23"), IOStandard("3.3-V LVTTL")), + ("key", 1, Pins("AD24"), IOStandard("3.3-V LVTTL")), + + # SPIFlash (W25Q64) + ("spiflash", 0, + # clk + Subsignal("cs_n", Pins("D5")), + Subsignal("clk", Pins("F6")), + Subsignal("mosi", Pins("E6")), + Subsignal("miso", Pins("D6")), + IOStandard("3.3-V LVTTL"), + ), + + # SDR SDRAM + ("sdram_clock", 0, Pins("J23"), IOStandard("3.3-V LVTTL")), + ("sdram", 0, + Subsignal("a", Pins( + "L25 L26 M25 M26 N22 N23 N24 M22", + "M24 L23 K26 L24 K23")), + Subsignal("ba", Pins("J25 J26")), + Subsignal("cs_n", Pins("H26")), + Subsignal("cke", Pins("K24")), + Subsignal("ras_n", Pins("H25")), + Subsignal("cas_n", Pins("G26")), + Subsignal("we_n", Pins("G25")), + Subsignal("dq", Pins( + "B25 B26 C25 C26 D25 D26 E25 E26", + "H23 G24 G22 F24 F23 E24 D24 C24")), + Subsignal("dm", Pins("F26 H24")), + IOStandard("3.3-V LVTTL") + ), +] + +# The connectors are named after the daughterboard, not the core board +# because on the different core boards the names vary, but on the +# daughterboard they stay the same, which we need to connect the +# daughterboard peripherals to the core board. +# On this board J2 is U5 and J3 is U4 +_connectors = [ + ("J2", { + # odd row even row + 7: "AF24", 8: "AF25", + 9: "AC21", 10: "AD21", + 11: "AE23", 12: "AF23", + 13: "AE22", 14: "AF22", + 15: "AD20", 16: "AE21", + 17: "AF20", 18: "AF21", + 19: "AE19", 20: "AF19", + 21: "AC19", 22: "AD19", + 23: "AE18", 24: "AF18", + 25: "AC18", 26: "AD18", + 27: "AE17", 28: "AF17", + 29: "AC17", 30: "AD17", + 31: "AF15", 32: "AF16", + 33: "AC16", 34: "AD16", + 35: "AE14", 36: "AE15", + 37: "AC15", 38: "AD15", + 39: "AC14", 40: "AD14", + 41: "AF11", 42: "AF12", + 43: "AC10", 44: "AD10", + 45: "AE9", 46: "AF9", + 47: "AF7", 48: "AF8", + 49: "AE7", 50: "AF6", + 51: "AE5", 52: "AE6", + 53: "AD5", 54: "AD6", + 55: "AF4", 56: "AF5", + 57: "AD3", 58: "AE3", + 59: "AC4", 60: "AD4", + }), + ("J3", { + # odd row even row + 7: "C21", 8: "B22", + 9: "B23", 10: "A23", + 11: "B21", 12: "A22", + 13: "C19", 14: "B19", + 15: "A21", 16: "A20", + 17: "A19", 18: "A18", + 19: "C17", 20: "B18", + 21: "C16", 22: "B17", + 23: "A17", 24: "A16", + 25: "B15", 26: "A15", + 27: "C15", 28: "C14", + 29: "C13", 30: "B13", + 31: "C12", 32: "C11", + 33: "A13", 34: "A12", + 35: "B11", 36: "A11", + 37: "B10", 38: "A10", + 39: "C10", 40: "B9", + 41: "A9", 42: "A8", + 43: "A7", 44: "A6", + 45: "B7", 46: "B6", + 47: "B5", 48: "A5", + 49: "B4", 50: "A4", + 51: "C5", 52: "C4", + 53: "A3", 54: "A2", + 55: "B2", 56: "B1", + 57: "D1", 58: "C1", + 59: "E2", 60: "E1", + }) +] + +# Platform ----------------------------------------------------------------------------------------- + +class Platform(AlteraPlatform): + default_clk_name = "clk50" + default_clk_period = 1e9/50e6 + core_resources = [ + ("user_led", 0, Pins("A25"), IOStandard("3.3-V LVTTL")), + ("user_led", 1, Pins("A24"), IOStandard("3.3-V LVTTL")), + ("serial", 0, + Subsignal("tx", Pins("J3:7"), IOStandard("3.3-V LVTTL")), + Subsignal("rx", Pins("J3:8"), IOStandard("3.3-V LVTTL")) + ), + ] + + def __init__(self, toolchain="quartus", with_daughterboard=False): + device = "EP4CGX150DF27I7" + io = _io + connectors = _connectors + + if with_daughterboard: + from litex_boards.platforms.qmtech_daughterboard import QMTechDaughterboard + daughterboard = QMTechDaughterboard(IOStandard("3.3-V LVTTL")) + io += daughterboard.io + connectors += daughterboard.connectors + else: + io += self.core_resources + + AlteraPlatform.__init__(self, device, io, connectors, toolchain=toolchain) + + if with_daughterboard: + # an ethernet pin takes K22, so make it available + self.add_platform_command("set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION \"USE AS REGULAR IO\"") + + def create_programmer(self): + return USBBlaster() + + def do_finalize(self, fragment): + AlteraPlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6) diff --git a/litex_boards/targets/qmtech_ep4cgx150.py b/litex_boards/targets/qmtech_ep4cgx150.py new file mode 100755 index 0000000..9afd5b0 --- /dev/null +++ b/litex_boards/targets/qmtech_ep4cgx150.py @@ -0,0 +1,177 @@ +#!/usr/bin/env python3 + +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2020 Basel Sayeh +# SPDX-License-Identifier: BSD-2-Clause + +from migen import * +from migen.genlib.resetsync import AsyncResetSynchronizer + +from litex.build.io import DDROutput + +from litex_boards.platforms import qmtech_ep4cgx150 + +from litex.soc.cores.clock import CycloneIVPLL +from litex.soc.integration.soc_core import * +from litex.soc.integration.builder import * +from litex.soc.cores.led import LedChaser + +from litedram.modules import W9825G6KH6 +from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY + +from litex.soc.cores.video import VideoVGAPHY +from liteeth.phy.mii import LiteEthPHYMII + +# CRG ---------------------------------------------------------------------------------------------- + +class _CRG(Module): + def __init__(self, platform, sys_clk_freq, with_ethernet, with_vga, sdram_rate="1:1"): + self.rst = Signal() + self.clock_domains.cd_sys = ClockDomain() + if sdram_rate == "1:2": + self.clock_domains.cd_sys2x = ClockDomain() + self.clock_domains.cd_sys2x_ps = ClockDomain() + else: + self.clock_domains.cd_sys_ps = ClockDomain() + + if with_ethernet: + self.clock_domains.cd_eth = ClockDomain() + if with_vga: + self.clock_domains.cd_vga = ClockDomain() + + # # # + + # Clk / Rst + clk50 = platform.request("clk50") + + # PLL + self.submodules.pll = pll = CycloneIVPLL(speedgrade="-6") + self.comb += pll.reset.eq(self.rst) + pll.register_clkin(clk50, 50e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + if sdram_rate == "1:2": + pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq) + # theoretically 90 degrees, but increase to relax timing + pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) + else: + pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) + + if with_ethernet: + pll.create_clkout(self.cd_eth, 25e6) + if with_vga: + pll.create_clkout(self.cd_vga, 40e6) + + # SDRAM clock + sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps") + self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk) + +# BaseSoC ------------------------------------------------------------------------------------------ + +class BaseSoC(SoCCore): + def __init__(self, sys_clk_freq=int(50e6), with_daughterboard=False, + with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, + with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False, + sdram_rate="1:1", **kwargs): + platform = qmtech_ep4cgx150.Platform(with_daughterboard=with_daughterboard) + + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on QMTECH EP4CGX150" + (" + Daughterboard" if with_daughterboard else ""), + **kwargs) + + # CRG -------------------------------------------------------------------------------------- + self.submodules.crg = _CRG(platform, sys_clk_freq, + with_ethernet = with_ethernet or with_etherbone, + with_vga = with_video_terminal or with_video_framebuffer, + sdram_rate = sdram_rate) + + # SDR SDRAM -------------------------------------------------------------------------------- + if not self.integrated_main_ram_size: + sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY + self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) + self.add_sdram("sdram", + phy = self.sdrphy, + module = W9825G6KH6(sys_clk_freq, sdram_rate), + l2_cache_size = kwargs.get("l2_size", 8192) + ) + + # Ethernet / Etherbone --------------------------------------------------------------------- + if with_ethernet or with_etherbone: + self.submodules.ethphy = LiteEthPHYMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) + if with_ethernet: + self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip) + if with_etherbone: + self.add_etherbone(phy=self.ethphy, ip_address=eth_ip) + + # Video ------------------------------------------------------------------------------------ + if with_video_terminal or with_video_framebuffer: + self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") + if with_video_terminal: + self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") + if with_video_framebuffer: + self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") + + # Leds ------------------------------------------------------------------------------------- + if with_led_chaser: + self.submodules.leds = LedChaser( + pads = platform.request_all("user_led"), + sys_clk_freq = sys_clk_freq) + +# Build -------------------------------------------------------------------------------------------- + +def main(): + from litex.soc.integration.soc import LiteXSoCArgumentParser + parser = LiteXSoCArgumentParser(description="LiteX SoC on QMTECH EP4CE15") + target_group = parser.add_argument_group(title="Target options") + target_group.add_argument("--build", action="store_true", help="Build bitstream.") + target_group.add_argument("--load", action="store_true", help="Load bitstream.") + target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") + target_group.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).") + target_group.add_argument("--with-daughterboard", action="store_true", help="Board plugged into the QMTech daughterboard.") + ethopts = target_group.add_mutually_exclusive_group() + ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.") + ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.") + target_group.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.") + target_group.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.") + sdopts = target_group.add_mutually_exclusive_group() + sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.") + sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.") + viopts = target_group.add_mutually_exclusive_group() + viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).") + viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA).") + + builder_args(parser) + soc_core_args(parser) + args = parser.parse_args() + + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + with_daughterboard = args.with_daughterboard, + with_ethernet = args.with_ethernet, + with_etherbone = args.with_etherbone, + eth_ip = args.eth_ip, + eth_dynamic_ip = args.eth_dynamic_ip, + with_video_terminal = args.with_video_terminal, + with_video_framebuffer = args.with_video_framebuffer, + sdram_rate = args.sdram_rate, + **soc_core_argdict(args) + ) + + if args.with_spi_sdcard: + soc.add_spi_sdcard() + if args.with_sdcard: + soc.add_sdcard() + + builder = Builder(soc, **builder_argdict(args)) + builder.build(run=args.build) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(builder.get_bitstream_filename(mode="sram")) + +if __name__ == "__main__": + main() From 53e9e0914e038bb9095772f5d41a390f86d8cb2c Mon Sep 17 00:00:00 2001 From: Hans Baier Date: Sat, 16 Apr 2022 15:00:01 +0700 Subject: [PATCH 2/2] qmtech_ep4cgx150 80MHz default works well --- litex_boards/targets/qmtech_ep4cgx150.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/targets/qmtech_ep4cgx150.py b/litex_boards/targets/qmtech_ep4cgx150.py index 9afd5b0..4dc558d 100755 --- a/litex_boards/targets/qmtech_ep4cgx150.py +++ b/litex_boards/targets/qmtech_ep4cgx150.py @@ -129,7 +129,7 @@ def main(): target_group = parser.add_argument_group(title="Target options") target_group.add_argument("--build", action="store_true", help="Build bitstream.") target_group.add_argument("--load", action="store_true", help="Load bitstream.") - target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") + target_group.add_argument("--sys-clk-freq", default=80e6, help="System clock frequency.") target_group.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).") target_group.add_argument("--with-daughterboard", action="store_true", help="Board plugged into the QMTech daughterboard.") ethopts = target_group.add_mutually_exclusive_group()