diff --git a/litex_boards/platforms/pano_logic_g2.py b/litex_boards/platforms/pano_logic_g2.py
index 1462537..76260bc 100755
--- a/litex_boards/platforms/pano_logic_g2.py
+++ b/litex_boards/platforms/pano_logic_g2.py
@@ -98,6 +98,7 @@ _io = [
         Subsignal("odt", Pins("J6"), IOStandard("SSTL18_II")),
     ),
     # Ethernet phy reset (clk125 is 25 Mhz instead of 125 Mhz if reset is active)
+    # See https://github.com/tomverbeure/panologic-g2#fpga-external-clocking-architecture
     ("gmii_rst_n", 0, Pins("R11"), IOStandard("LVCMOS33")),
 
 ]