From 0648c041589cb1c8452932483138996c0ec6a714 Mon Sep 17 00:00:00 2001 From: Skip Hansen Date: Mon, 25 May 2020 14:48:24 -0700 Subject: [PATCH] Updated comment, added link to clocking documentation. --- litex_boards/platforms/pano_logic_g2.py | 1 + 1 file changed, 1 insertion(+) diff --git a/litex_boards/platforms/pano_logic_g2.py b/litex_boards/platforms/pano_logic_g2.py index 1462537..76260bc 100755 --- a/litex_boards/platforms/pano_logic_g2.py +++ b/litex_boards/platforms/pano_logic_g2.py @@ -98,6 +98,7 @@ _io = [ Subsignal("odt", Pins("J6"), IOStandard("SSTL18_II")), ), # Ethernet phy reset (clk125 is 25 Mhz instead of 125 Mhz if reset is active) + # See https://github.com/tomverbeure/panologic-g2#fpga-external-clocking-architecture ("gmii_rst_n", 0, Pins("R11"), IOStandard("LVCMOS33")), ]