From 06edf48897606483c407ec93d23c1a4cf54b42bc Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 2 Jun 2020 13:45:05 +0200 Subject: [PATCH] targets: rename gateware-toolchain parameter to toolchain. --- litex_boards/targets/camlink_4k.py | 2 +- litex_boards/targets/ecp5_evn.py | 2 +- litex_boards/targets/hadbadge.py | 2 +- litex_boards/targets/orangecrab.py | 2 +- litex_boards/targets/simple.py | 6 +++--- litex_boards/targets/trellisboard.py | 2 +- litex_boards/targets/ulx3s.py | 2 +- litex_boards/targets/versa_ecp5.py | 2 +- 8 files changed, 10 insertions(+), 10 deletions(-) diff --git a/litex_boards/targets/camlink_4k.py b/litex_boards/targets/camlink_4k.py index 7f1789c..f6afa1c 100755 --- a/litex_boards/targets/camlink_4k.py +++ b/litex_boards/targets/camlink_4k.py @@ -108,7 +108,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Cam Link 4K") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") + parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) diff --git a/litex_boards/targets/ecp5_evn.py b/litex_boards/targets/ecp5_evn.py index 70ab8df..8b81ad7 100755 --- a/litex_boards/targets/ecp5_evn.py +++ b/litex_boards/targets/ecp5_evn.py @@ -64,7 +64,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on ECP5 Evaluation Board") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") + parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") builder_args(parser) soc_core_args(parser) parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default=60MHz)") diff --git a/litex_boards/targets/hadbadge.py b/litex_boards/targets/hadbadge.py index 5a81eef..2e5cd30 100755 --- a/litex_boards/targets/hadbadge.py +++ b/litex_boards/targets/hadbadge.py @@ -80,7 +80,7 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Hackaday Badge") parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") + parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") parser.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency (default=48MHz)") builder_args(parser) soc_sdram_args(parser) diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py index 5529cbb..98cf0a1 100755 --- a/litex_boards/targets/orangecrab.py +++ b/litex_boards/targets/orangecrab.py @@ -129,7 +129,7 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on OrangeCrab") parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") + parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) diff --git a/litex_boards/targets/simple.py b/litex_boards/targets/simple.py index 70872bb..0954a1e 100755 --- a/litex_boards/targets/simple.py +++ b/litex_boards/targets/simple.py @@ -47,12 +47,12 @@ def main(): soc_core_args(parser) parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("platform", help="Module name of the platform to build for") - parser.add_argument("--gateware-toolchain", default=None, help="FPGA gateware toolchain used for build") + parser.add_argument("--toolchain", default=None, help="FPGA gateware toolchain used for build") args = parser.parse_args() platform_module = importlib.import_module(args.platform) - if args.gateware_toolchain is not None: - platform = platform_module.Platform(toolchain=args.gateware_toolchain) + if args.toolchain is not None: + platform = platform_module.Platform(toolchain=args.toolchain) else: platform = platform_module.Platform() soc = BaseSoC(platform, with_ethernet=args.with_ethernet, **soc_core_argdict(args)) diff --git a/litex_boards/targets/trellisboard.py b/litex_boards/targets/trellisboard.py index ce872e0..a583054 100755 --- a/litex_boards/targets/trellisboard.py +++ b/litex_boards/targets/trellisboard.py @@ -125,7 +125,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Trellis Board") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") + parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) diff --git a/litex_boards/targets/ulx3s.py b/litex_boards/targets/ulx3s.py index 6bbe488..6fec867 100755 --- a/litex_boards/targets/ulx3s.py +++ b/litex_boards/targets/ulx3s.py @@ -102,7 +102,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") + parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") parser.add_argument("--device", dest="device", default="LFE5U-45F", help="FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F") parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default=50MHz)") parser.add_argument("--sdram-module", default="MT48LC16M16", help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)") diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py index 293c467..5e0e2be 100755 --- a/litex_boards/targets/versa_ecp5.py +++ b/litex_boards/targets/versa_ecp5.py @@ -119,7 +119,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Versa ECP5") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") + parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") builder_args(parser) soc_sdram_args(parser) trellis_args(parser)