From 0854a5d23484c1dbed27d370cf697016450cfc7d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 16 Sep 2021 18:02:55 +0200 Subject: [PATCH] litex_m2_baseboard: Add Ethernet/Etherbone support. --- litex_boards/platforms/litex_m2_baseboard.py | 18 +++++++++++++ litex_boards/targets/litex_m2_baseboard.py | 27 +++++++++++++++++--- 2 files changed, 41 insertions(+), 4 deletions(-) diff --git a/litex_boards/platforms/litex_m2_baseboard.py b/litex_boards/platforms/litex_m2_baseboard.py index 440b50e..5a3ec13 100644 --- a/litex_boards/platforms/litex_m2_baseboard.py +++ b/litex_boards/platforms/litex_m2_baseboard.py @@ -24,6 +24,24 @@ _io = [ # Buttons ("user_btn", 0, Pins("M19"), IOStandard("LVCMOS33")), ("user_btn", 1, Pins("M20"), IOStandard("LVCMOS33")), + + # RGMII Ethernet + ("eth_clocks", 0, + Subsignal("tx", Pins("M1")), + Subsignal("rx", Pins("H2")), + IOStandard("LVCMOS25") + ), + ("eth", 0, + Subsignal("int_n", Pins("F1")), + Subsignal("rst_n", Pins("J3")), + Subsignal("mdio", Pins("G2")), + Subsignal("mdc", Pins("G1")), + Subsignal("rx_ctl", Pins("H1")), + Subsignal("rx_data", Pins("J1 K2 K1 L2"), Misc("PULLMODE=UP")), # RGMII mode - Advertise all capabilities. + Subsignal("tx_ctl", Pins("L1")), + Subsignal("tx_data", Pins("P1 P2 N1 N2")), + IOStandard("LVCMOS25") + ), ] # Connectors --------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/litex_m2_baseboard.py b/litex_boards/targets/litex_m2_baseboard.py index 156b9ec..3c616fc 100755 --- a/litex_boards/targets/litex_m2_baseboard.py +++ b/litex_boards/targets/litex_m2_baseboard.py @@ -20,13 +20,16 @@ from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * +from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII + # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): def __init__(self, platform, sys_clk_freq): self.rst = Signal() - self.clock_domains.cd_por = ClockDomain(reset_less=True) - self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_por = ClockDomain(reset_less=True) + self.clock_domains.cd_sys = ClockDomain() + # # # # Clk / Rst @@ -48,7 +51,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(75e6), **kwargs): + def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, with_etherbone=False, **kwargs): platform = litex_m2_baseboard.Platform(toolchain="trellis") # SoCCore ---------------------------------------------------------------------------------- @@ -60,6 +63,17 @@ class BaseSoC(SoCCore): # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) + # Ethernet / Etherbone --------------------------------------------------------------------- + if with_ethernet or with_etherbone: + self.submodules.ethphy = LiteEthPHYRGMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth"), + rx_delay = 0e-9) + if with_ethernet: + self.add_ethernet(phy=self.ethphy) + if with_etherbone: + self.add_etherbone(phy=self.ethphy) + # Build -------------------------------------------------------------------------------------------- def main(): @@ -68,13 +82,18 @@ def main(): parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--flash", action="store_true", help="Flash bitstream to SPI Flash") parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)") + ethopts = parser.add_mutually_exclusive_group() + ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") builder_args(parser) soc_core_args(parser) trellis_args(parser) args = parser.parse_args() soc = BaseSoC( - sys_clk_freq = int(float(args.sys_clk_freq)), + sys_clk_freq = int(float(args.sys_clk_freq)), + with_ethernet = args.with_ethernet, + with_etherbone = args.with_etherbone, **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args))