From 08a79fa3ac68d1ddff0ba58432e86351efbbf100 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 15 Feb 2022 10:58:38 +0100 Subject: [PATCH] lattice_ecp5_vip: Minor cleanups, fix CI. --- litex_boards/platforms/lattice_ecp5_vip.py | 15 ++++---- litex_boards/targets/lattice_ecp5_evn.py | 4 +-- litex_boards/targets/lattice_ecp5_vip.py | 42 +++++++++++----------- 3 files changed, 30 insertions(+), 31 deletions(-) diff --git a/litex_boards/platforms/lattice_ecp5_vip.py b/litex_boards/platforms/lattice_ecp5_vip.py index 35acd6d..d9d88c5 100644 --- a/litex_boards/platforms/lattice_ecp5_vip.py +++ b/litex_boards/platforms/lattice_ecp5_vip.py @@ -2,6 +2,7 @@ # This file is part of LiteX-Boards. # # Copyright (c) 2019 Arnaud Durand +# Copyright (c) 2022 Martin Hubacek @hubmartin (Twitter) # SPDX-License-Identifier: BSD-2-Clause from litex.build.generic_platform import * @@ -14,11 +15,11 @@ import os _io = [ # Clk / Rst - ("clk27", 0, Pins("E17"), IOStandard("LVCMOS33")), ## - ("clk100", 0, Pins("C5"), IOStandard("LVDS")), ## + ("clk27", 0, Pins("E17"), IOStandard("LVCMOS33")), + ("clk100", 0, Pins("C5"), IOStandard("LVDS")), ("ext_clk50", 0, Pins("B11"), IOStandard("LVCMOS33")), ("ext_clk50_en", 0, Pins("C11"), IOStandard("LVCMOS33")), - ("rst_n", 0, Pins("AH1"), IOStandard("LVCMOS33")),## + ("rst_n", 0, Pins("AH1"), IOStandard("LVCMOS33")), # Leds ("user_led", 0, Pins("AG30"), IOStandard("LVCMOS25")), @@ -115,8 +116,8 @@ _io = [ # Platform ----------------------------------------------------------------------------------------- class Platform(LatticePlatform): - default_clk_name = "clk12" - default_clk_period = 1e9/12e6 + default_clk_name = "clk27" + default_clk_period = 1e9/27e6 def __init__(self, toolchain="trellis", **kwargs): LatticePlatform.__init__(self, "LFE5UM-85F-8BG756", _io, toolchain=toolchain, **kwargs) @@ -140,5 +141,5 @@ class Platform(LatticePlatform): def do_finalize(self, fragment): LatticePlatform.do_finalize(self, fragment) - self.add_period_constraint(self.lookup_request("clk12", loose=True), 1e9/12e6) - self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6) + self.add_period_constraint(self.lookup_request("clk27", loose=True), 1e9/27e6) + self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6) diff --git a/litex_boards/targets/lattice_ecp5_evn.py b/litex_boards/targets/lattice_ecp5_evn.py index de4f623..ae27c22 100755 --- a/litex_boards/targets/lattice_ecp5_evn.py +++ b/litex_boards/targets/lattice_ecp5_evn.py @@ -28,7 +28,7 @@ class _CRG(Module): # # # - # clk / rst + # Clk / Rst. clk = clk12 = platform.request("clk12") rst_n = platform.request("rst_n") if x5_clk_freq is not None: @@ -36,7 +36,7 @@ class _CRG(Module): self.comb += platform.request("ext_clk50_en").eq(1) platform.add_period_constraint(clk50, 1e9/x5_clk_freq) - # pll + # PLL. self.submodules.pll = pll = ECP5PLL() self.comb += pll.reset.eq(~rst_n | self.rst) pll.register_clkin(clk, x5_clk_freq or 12e6) diff --git a/litex_boards/targets/lattice_ecp5_vip.py b/litex_boards/targets/lattice_ecp5_vip.py index 4a054a8..413b071 100755 --- a/litex_boards/targets/lattice_ecp5_vip.py +++ b/litex_boards/targets/lattice_ecp5_vip.py @@ -29,7 +29,7 @@ from litex.soc.cores.bitbang import I2CMaster # CRG ---------------------------------------------------------------------------------------------- -class _CRG_VERSA(Module): +class _CRG(Module): def __init__(self, platform, sys_clk_freq): self.rst = Signal() self.clock_domains.cd_init = ClockDomain() @@ -85,11 +85,11 @@ class _CRG_VERSA(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - #mem_map = {**SoCCore.mem_map, **{"spiflash": 0x1000000}} def __init__(self, sys_clk_freq=int(50e6), toolchain="trellis", - with_led_chaser=True, - with_video_terminal=True, - with_video_framebuffer=False,**kwargs): + with_led_chaser = True, + with_video_terminal = True, + with_video_framebuffer = False, + **kwargs): platform = ecp5_vip.Platform(toolchain=toolchain) #bios_flash_offset = 0x400000 @@ -101,27 +101,24 @@ class BaseSoC(SoCCore): # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on ECP5 Evaluation Board", - #ident_version = True, #integrated_main_ram_size = 0x4000, - integrated_main_ram_size = 0, + #integrated_main_ram_size = 0, **kwargs) # CRG -------------------------------------------------------------------------------------- - crg_cls = _CRG_VERSA - self.submodules.crg = crg_cls(platform, sys_clk_freq) + self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- - if crg_cls == _CRG_VERSA: - self.submodules.ddrphy = ECP5DDRPHY( - platform.request("ddram"), - sys_clk_freq=sys_clk_freq) - self.comb += self.crg.stop.eq(self.ddrphy.init.stop) - self.comb += self.crg.reset.eq(self.ddrphy.init.reset) - self.add_sdram("sdram", - phy = self.ddrphy, - module = MT41K64M16(sys_clk_freq, "1:2"), # Not entirely MT41J64M16 but similar and works(c) - l2_cache_size = kwargs.get("l2_size", 8192), - ) + self.submodules.ddrphy = ECP5DDRPHY( + platform.request("ddram"), + sys_clk_freq=sys_clk_freq) + self.comb += self.crg.stop.eq(self.ddrphy.init.stop) + self.comb += self.crg.reset.eq(self.ddrphy.init.reset) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT41K64M16(sys_clk_freq, "1:2"), # Not entirely MT41J64M16 but similar and works(c) + l2_cache_size = kwargs.get("l2_size", 8192), + ) # Video ------------------------------------------------------------------------------------ if with_video_terminal or with_video_framebuffer: @@ -193,7 +190,7 @@ class BaseSoC(SoCCore): # # Add ROM linker region -------------------------------------------------------------------- # self.bus.add_region("rom", SoCRegion( - # origin = self.mem_map["spiflash"] + bios_flash_offset, + # origin = self.bus.regions["spiflash"].origin + bios_flash_offset, # size = (16-4)*1024*1024, # linker = True) # ) @@ -210,7 +207,8 @@ def main(): soc_core_args(parser) args = parser.parse_args() - soc = BaseSoC(toolchain=args.toolchain, + soc = BaseSoC( + toolchain = args.toolchain, sys_clk_freq = int(float(args.sys_clk_freq)), **soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args))