test/test_targets: update.
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@ -35,6 +35,7 @@ class TestTargets(unittest.TestCase):
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platforms.append("minispartan6")
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platforms.append("minispartan6")
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platforms.append("pipistrello")
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platforms.append("pipistrello")
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platforms.append("sp605")
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platforms.append("sp605")
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platforms.append("pano_logic_g2")
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# Xilinx Spartan7
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# Xilinx Spartan7
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platforms.append("arty_s7")
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platforms.append("arty_s7")
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@ -65,9 +66,11 @@ class TestTargets(unittest.TestCase):
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# Xilinx Zynq-7000
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# Xilinx Zynq-7000
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platforms.append("zedboard")
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platforms.append("zedboard")
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platforms.append("zybo_z7")
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# Xilinx Zynq Ultrascale+
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# Xilinx Zynq Ultrascale+
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platforms.append("zcu104")
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platforms.append("zcu104")
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platforms.append("mercury_xu5")
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# Xilinx Virtex Ultrascale+
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# Xilinx Virtex Ultrascale+
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platforms.append("vcu118")
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platforms.append("vcu118")
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@ -94,6 +97,7 @@ class TestTargets(unittest.TestCase):
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platforms.append("fomu_hacker")
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platforms.append("fomu_hacker")
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platforms.append("fomu_pvt")
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platforms.append("fomu_pvt")
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platforms.append("tinyfpga_bx")
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platforms.append("tinyfpga_bx")
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platforms.append("icebreaker")
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# Lattice MachXO2
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# Lattice MachXO2
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platforms.append("machxo3")
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platforms.append("machxo3")
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@ -106,6 +110,15 @@ class TestTargets(unittest.TestCase):
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platforms.append("ulx3s")
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platforms.append("ulx3s")
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platforms.append("versa_ecp5")
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platforms.append("versa_ecp5")
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platforms.append("colorlight_5a_75b")
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platforms.append("colorlight_5a_75b")
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platforms.append("colorlight_5a_75e")
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platforms.append("camlink_4k")
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# Lattice Crosslink NX
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platforms.append("crosslink_nx_evn")
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platforms.append("crosslink_nx_vip")
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# Gowin
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platforms.append("tec0117")
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# Microsemi PolarFire
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# Microsemi PolarFire
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platforms.append("avalanche")
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platforms.append("avalanche")
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