diff --git a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py
index 2a66da0..af7fd35 100755
--- a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py
+++ b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py
@@ -75,6 +75,7 @@ class BaseSoC(SoCCore):
                 memtype         = "DDR4",
                 iodelay_clk_freq = iodelay_clk_freq,
                 sys_clk_freq     = sys_clk_freq,
+                cmd_latency      = 1,
                 is_rdimm         = True,
             )
             self.add_sdram("sdram",