From 0b80890119b3db65fb63d71687cba3c182e493f8 Mon Sep 17 00:00:00 2001 From: Piotr Binkowski Date: Wed, 26 Jan 2022 15:57:34 +0100 Subject: [PATCH] antmicro_datacenter: add 1 cycle of latency for RCD IC --- litex_boards/targets/antmicro_datacenter_ddr4_test_board.py | 1 + 1 file changed, 1 insertion(+) diff --git a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py index 2a66da0..af7fd35 100755 --- a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py +++ b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py @@ -75,6 +75,7 @@ class BaseSoC(SoCCore): memtype = "DDR4", iodelay_clk_freq = iodelay_clk_freq, sys_clk_freq = sys_clk_freq, + cmd_latency = 1, is_rdimm = True, ) self.add_sdram("sdram",