From f66860c2015bb684d3789f3ce7a996e05521960b Mon Sep 17 00:00:00 2001 From: Alessandro Comodi Date: Mon, 7 Dec 2020 16:46:20 +0100 Subject: [PATCH] zybo_z7: fix clock pin constraint Signed-off-by: Alessandro Comodi --- litex_boards/platforms/zybo_z7.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/platforms/zybo_z7.py b/litex_boards/platforms/zybo_z7.py index f9736af..9fc135d 100644 --- a/litex_boards/platforms/zybo_z7.py +++ b/litex_boards/platforms/zybo_z7.py @@ -11,7 +11,7 @@ from litex.build.xilinx import XilinxPlatform, VivadoProgrammer _io = [ # Clk / Rst - ("clk125", 0, Pins("L16"), IOStandard("LVCMOS33")), + ("clk125", 0, Pins("K17"), IOStandard("LVCMOS33")), # Leds ("user_led", 0, Pins("M14"), IOStandard("LVCMOS33")),