From 53007b3cb6ef232b54ea9ad71fa9c3a1dcfe3b77 Mon Sep 17 00:00:00 2001 From: Sergiu Mosanu Date: Tue, 1 Feb 2022 14:24:48 -0500 Subject: [PATCH 1/3] ignore ip directory and files --- .gitignore | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.gitignore b/.gitignore index cf301cb..979f008 100644 --- a/.gitignore +++ b/.gitignore @@ -97,3 +97,6 @@ ENV/ # support library for EOS-S3 (downloaded when needed) litex_boards/targets/libeos/ + +# ip files used during build +litex_boards/targets/ip/ From 5a0f69502be6f4c7b1cdf4c77f58621f0d96b8dc Mon Sep 17 00:00:00 2001 From: Sergiu Mosanu Date: Tue, 8 Feb 2022 12:18:38 -0500 Subject: [PATCH 2/3] enable use of HBM for linux boot --- README.md | 2 +- litex_boards/targets/xilinx_alveo_u280.py | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 190c378..100772c 100644 --- a/README.md +++ b/README.md @@ -96,7 +96,7 @@ PCIe accelerators boards that you could use to accelerate your applications, Lit | ForestKitten33 | Xilinx Ultrascale+ | XCVU33P | 125MHz | PCIe | 2 x 1024-bit 4GB HBM2*| Gen3 X16 | ? | | BCU1525 | Xilinx Ultrascale+ | XCVU9P | 125MHz | PCIe | 4 x 64-bit DDR4 DIMM | Gen3 X16 | ? | | AlveoU250 | Xilinx Ultrascale+ | XCU250 | 125MHz | PCIe | 4 x 64-bit DDR4 DIMM | Gen2 X16 | ? | -| AlveoU280 | Xilinx Ultrascale+ | XCU280-ES1 | 150MHz | PCIe* | 2 x 64-bit DDR4 DIMM
2 x 1024-bit 4GB HBM2* | Gen2 X16 | ? | +| AlveoU280 | Xilinx Ultrascale+ | XCU280-ES1 | 150MHz | PCIe* | 2 x 64-bit 16GB DDR4 DIMM*
2 x 1024-bit 4GB HBM2 | Gen2 X16 | ? | \* Present on the board but not yet supported or validated with LiteX. diff --git a/litex_boards/targets/xilinx_alveo_u280.py b/litex_boards/targets/xilinx_alveo_u280.py index b222e69..f441390 100755 --- a/litex_boards/targets/xilinx_alveo_u280.py +++ b/litex_boards/targets/xilinx_alveo_u280.py @@ -220,6 +220,9 @@ class BaseSoC(SoCCore): axi_lite_hbm = AXILiteInterface(data_width=256, address_width=33) self.submodules += AXILite2AXI(axi_lite_hbm, axi_hbm) self.bus.add_slave(f"hbm{i}", axi_lite_hbm, SoCRegion(origin=0x4000_0000 + 0x1000_0000*i, size=0x1000_0000)) # 256MB. + # Link HBM2 channel 0 as main RAM + self.bus.add_region("main_ram", SoCRegion(origin=0x4000_0000, size=0x1000_0000, linker=True)) # 256MB. + else: # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: From 7ed633dc4bd6465ad27460ec2e354f92f8dc3b08 Mon Sep 17 00:00:00 2001 From: Sergiu Mosanu Date: Tue, 8 Feb 2022 12:54:34 -0500 Subject: [PATCH 3/3] add guideline for serial interface --- litex_boards/targets/xilinx_alveo_u280.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/litex_boards/targets/xilinx_alveo_u280.py b/litex_boards/targets/xilinx_alveo_u280.py index f441390..be6751c 100755 --- a/litex_boards/targets/xilinx_alveo_u280.py +++ b/litex_boards/targets/xilinx_alveo_u280.py @@ -9,6 +9,9 @@ # # SPDX-License-Identifier: BSD-2-Clause +# To interface via the serial port use: +# lxterm /dev/ttyUSBx --speed=115200 + import argparse, os from migen import *