diff --git a/litex_boards/targets/digilent_cmod_a7.py b/litex_boards/targets/digilent_cmod_a7.py index 15ed684..a8b0473 100755 --- a/litex_boards/targets/digilent_cmod_a7.py +++ b/litex_boards/targets/digilent_cmod_a7.py @@ -115,7 +115,8 @@ def addAsyncSram(soc, platform, name, origin, size): class BaseSoC(SoCCore): def __init__(self, variant="a7-35", toolchain="vivado", - sys_clk_freq=int(100e6), + sys_clk_freq=int(100e6), + with_led_chaser=True, ident_version=True, with_jtagbone=True, with_mapped_flash=False, @@ -136,9 +137,10 @@ class BaseSoC(SoCCore): addAsyncSram(self,platform,"main_ram",0x40000000,512*1024) # Leds ------------------------------------------------------------------------------------- - self.submodules.leds = LedChaser( - pads = platform.request_all("user_led"), - sys_clk_freq = sys_clk_freq) + if with_led_chaser: + self.submodules.leds = LedChaser( + pads = platform.request_all("user_led"), + sys_clk_freq = sys_clk_freq) # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/digilent_nexys4.py b/litex_boards/targets/digilent_nexys4.py index ea2e736..b077588 100755 --- a/litex_boards/targets/digilent_nexys4.py +++ b/litex_boards/targets/digilent_nexys4.py @@ -168,7 +168,7 @@ def addCellularRAM(soc, platform, name, origin): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, with_etherbone=False, with_video_terminal=False, with_video_framebuffer=False, **kwargs): + def __init__(self, sys_clk_freq=int(75e6), with_led_chaser=True, with_ethernet=False, with_etherbone=False, with_video_terminal=False, with_video_framebuffer=False, **kwargs): platform = digilent_nexys4.Platform() # SoCCore ----------------------------------_----------------------------------------------- @@ -201,9 +201,10 @@ class BaseSoC(SoCCore): self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") # Leds ------------------------------------------------------------------------------------- - self.submodules.leds = LedChaser( - pads = platform.request_all("user_led"), - sys_clk_freq = sys_clk_freq) + if with_led_chaser: + self.submodules.leds = LedChaser( + pads = platform.request_all("user_led"), + sys_clk_freq = sys_clk_freq) # Build -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/micronova_mercury2.py b/litex_boards/targets/micronova_mercury2.py index 606ee7a..3f3b26e 100755 --- a/litex_boards/targets/micronova_mercury2.py +++ b/litex_boards/targets/micronova_mercury2.py @@ -112,11 +112,11 @@ class BaseSoC(SoCCore): def __init__(self, variant="a7-35", toolchain="vivado", - sys_clk_freq=int(100e6), + sys_clk_freq=int(100e6), + with_led_chaser=True, ident_version=True, with_jtagbone=True, with_mapped_flash=False, - enable_leds = True, **kwargs): platform = micronova_mercury2.Platform() @@ -136,10 +136,10 @@ class BaseSoC(SoCCore): #self.add_timer() # Leds ------------------------------------------------------------------------------------- - if enable_leds: - self.submodules.leds = LedChaser( - pads = platform.request_all("user_led"), - sys_clk_freq = sys_clk_freq) + if with_led_chaser: + self.submodules.leds = LedChaser( + pads = platform.request_all("user_led"), + sys_clk_freq = sys_clk_freq) # Build --------------------------------------------------------------------------------------------