From 0d549a8c89b2b3abf01aafeb9451279d01a5d6e8 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 24 May 2020 11:22:02 +0200 Subject: [PATCH] platforms: add forest_kitten_33 initial platform suppport. --- litex_boards/platforms/forest_kitten_33.py | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 litex_boards/platforms/forest_kitten_33.py diff --git a/litex_boards/platforms/forest_kitten_33.py b/litex_boards/platforms/forest_kitten_33.py new file mode 100644 index 0000000..e9a5602 --- /dev/null +++ b/litex_boards/platforms/forest_kitten_33.py @@ -0,0 +1,60 @@ +# This file is Copyright (c) 2020 Florent Kermarrec +# License: BSD + +# The Forest Kitten 33 is a cryptocurrency mining accelerator card from SQRL that can be repurposed +# as a generic FPGA PCIe development board: http://www.squirrelsresearch.com/forest-kitten-33 + +from litex.build.generic_platform import * +from litex.build.xilinx import XilinxPlatform, VivadoProgrammer + +# IOs ---------------------------------------------------------------------------------------------- + +_io = [ + ("clk200", 0, + Subsignal("p", Pins("BC26"), IOStandard("LVDS")), + Subsignal("n", Pins("BC27"), IOStandard("LVDS")) + ), + + ("user_led", 0, Pins("BD25"), IOStandard("LVCMOS18")), + ("user_led", 1, Pins("BE26"), IOStandard("LVCMOS18")), + ("user_led", 2, Pins("BD23"), IOStandard("LVCMOS18")), + ("user_led", 3, Pins("BF26"), IOStandard("LVCMOS18")), + ("user_led", 4, Pins("BC25"), IOStandard("LVCMOS18")), + ("user_led", 5, Pins("BB26"), IOStandard("LVCMOS18")), + ("user_led", 6, Pins("BB25"), IOStandard("LVCMOS18")), + + ("i2c", + Subsignal("scl", Pins("BB24"), IOStandard("LVCMOS18"), Misc("DRIVE=8")), + Subsignal("sda", Pins("BA24"), IOStandard("LVCMOS18"), Misc("DRIVE=8")), + ), + + ("pcie_x16", 0, + Subsignal("rst_n", Pins("BE24"), IOStandard("LVCMOS18")), + Subsignal("clk_p", Pins("AD9")), + Subsignal("clk_n", Pins("AD8")), + Subsignal("rx_p", Pins("AL2 AM4 AK4 AN2 AP4 AR2 AT4 AU2 AV4 AW2 BA2 BC2 AY4 BB4 BD4 BE6")), + Subsignal("rx_n", Pins("AL1 AM3 AK3 AN1 AP3 AR1 AT3 AU1 AV3 AW1 BA1 BC1 AY3 BB3 BD3 BE5")), + Subsignal("tx_p", Pins("Y5 AA7 AB5 AC7 AD5 AF5 AE7 AH5 AG7 AJ7 AL7 AM9 AN7 AP9 AR7 AT9")), + Subsignal("tx_n", Pins("Y4 AA6 AB4 AC6 AD4 AF4 AE6 AH4 AG6 AJ6 AL6 AM8 AN6 AP8 AR6 AT8")), + ), +] + +# Platform ----------------------------------------------------------------------------------------- + +class Platform(XilinxPlatform): + default_clk_name = "clk200" + default_clk_period = 1e9/200e6 + + def __init__(self): + XilinxPlatform.__init__(self, "xcvu33p-fsvh2104-2L-e", _io, toolchain="vivado") + + def create_programmer(self): + return VivadoProgrammer() + + def do_finalize(self, fragment): + XilinxPlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6) + # Shutdown on overheatng + self.add_platform_command("set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]") + # Reduce programming time + self.add_platform_command("set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]")