From 88f7d5f019b0e26d470923bb30514ff568c8f111 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Tue, 8 Oct 2024 13:27:59 +0200 Subject: [PATCH 1/2] finix_trion_t20_bga256_dev_kit: fix ClockSignal MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Fin Maaß --- litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py b/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py index 92fe6e2..04db654 100755 --- a/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py +++ b/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py @@ -69,7 +69,7 @@ class BaseSoC(SoCCore): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size and sys_clk_freq <= 50e6 : - self.specials += ClkOutput(ClockSignal(self.cd_sys_ps), platform.request("sdram_clock")) + self.specials += ClkOutput(ClockSignal("sys_ps"), platform.request("sdram_clock")) self.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", From 362a28b72ac6adc5dcd8a24e34520c84ef65969f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Tue, 8 Oct 2024 13:40:30 +0200 Subject: [PATCH 2/2] efinix: fix reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fix reset on all efinix boards. To reset the PLL a pulse is needed, which has to be driven by a clock that is not generated by the PLL. Signed-off-by: Fin Maaß --- litex_boards/platforms/efinix_t8f81_dev_kit.py | 1 + .../efinix_titanium_ti60_f225_dev_kit.py | 1 + .../efinix_trion_t120_bga576_dev_kit.py | 1 + .../platforms/efinix_trion_t20_bga256_dev_kit.py | 1 + .../platforms/efinix_trion_t20_mipi_dev_kit.py | 1 + litex_boards/platforms/efinix_xyloni_dev_kit.py | 1 + .../platforms/jungle_electronics_fireant.py | 1 + litex_boards/targets/efinix_t8f81_dev_kit.py | 14 ++++++++++++-- .../targets/efinix_ti375_c529_dev_kit.py | 16 +++++++++++++--- .../targets/efinix_titanium_ti60_f225_dev_kit.py | 14 ++++++++++++-- .../targets/efinix_trion_t120_bga576_dev_kit.py | 16 ++++++++++++---- .../targets/efinix_trion_t20_bga256_dev_kit.py | 7 +++++-- .../targets/efinix_trion_t20_mipi_dev_kit.py | 14 ++++++++++++-- litex_boards/targets/efinix_xyloni_dev_kit.py | 14 ++++++++++++-- .../targets/jungle_electronics_fireant.py | 14 ++++++++++++-- 15 files changed, 97 insertions(+), 19 deletions(-) diff --git a/litex_boards/platforms/efinix_t8f81_dev_kit.py b/litex_boards/platforms/efinix_t8f81_dev_kit.py index 870d445..983b680 100644 --- a/litex_boards/platforms/efinix_t8f81_dev_kit.py +++ b/litex_boards/platforms/efinix_t8f81_dev_kit.py @@ -52,6 +52,7 @@ _connectors = [ class Platform(EfinixPlatform): default_clk_name = "clk33" + default_clk_freq = 33.333e6 default_clk_period = 1e9/33.333e6 def __init__(self, toolchain="efinity"): diff --git a/litex_boards/platforms/efinix_titanium_ti60_f225_dev_kit.py b/litex_boards/platforms/efinix_titanium_ti60_f225_dev_kit.py index a1620e9..71cd848 100644 --- a/litex_boards/platforms/efinix_titanium_ti60_f225_dev_kit.py +++ b/litex_boards/platforms/efinix_titanium_ti60_f225_dev_kit.py @@ -183,6 +183,7 @@ def rgmii_ethernet_qse_ios(con, n=""): class Platform(EfinixPlatform): default_clk_name = "clk25" + default_clk_freq = 25e6 default_clk_period = 1e9/50e6 def __init__(self, toolchain="efinity"): diff --git a/litex_boards/platforms/efinix_trion_t120_bga576_dev_kit.py b/litex_boards/platforms/efinix_trion_t120_bga576_dev_kit.py index 81b7f6f..a0e19c2 100644 --- a/litex_boards/platforms/efinix_trion_t120_bga576_dev_kit.py +++ b/litex_boards/platforms/efinix_trion_t120_bga576_dev_kit.py @@ -174,6 +174,7 @@ def usb_pmod_io(pmod): class Platform(EfinixPlatform): default_clk_name = "clk40" + default_clk_freq = 40e6 default_clk_period = 1e9/40e6 def __init__(self, toolchain="efinity"): diff --git a/litex_boards/platforms/efinix_trion_t20_bga256_dev_kit.py b/litex_boards/platforms/efinix_trion_t20_bga256_dev_kit.py index e3f88df..04435f7 100644 --- a/litex_boards/platforms/efinix_trion_t20_bga256_dev_kit.py +++ b/litex_boards/platforms/efinix_trion_t20_bga256_dev_kit.py @@ -113,6 +113,7 @@ _connectors = [ class Platform(EfinixPlatform): default_clk_name = "clk50" + default_clk_freq = 50e6 default_clk_period = 1e9/50e6 def __init__(self, toolchain="efinity"): diff --git a/litex_boards/platforms/efinix_trion_t20_mipi_dev_kit.py b/litex_boards/platforms/efinix_trion_t20_mipi_dev_kit.py index 8746b3b..15b7e2c 100644 --- a/litex_boards/platforms/efinix_trion_t20_mipi_dev_kit.py +++ b/litex_boards/platforms/efinix_trion_t20_mipi_dev_kit.py @@ -64,6 +64,7 @@ _connectors = [] class Platform(EfinixPlatform): default_clk_name = "clk50" + default_clk_freq = 50e6 default_clk_period = 1e9/50e6 def __init__(self, toolchain="efinity"): diff --git a/litex_boards/platforms/efinix_xyloni_dev_kit.py b/litex_boards/platforms/efinix_xyloni_dev_kit.py index 350f09b..d11c7b5 100644 --- a/litex_boards/platforms/efinix_xyloni_dev_kit.py +++ b/litex_boards/platforms/efinix_xyloni_dev_kit.py @@ -71,6 +71,7 @@ _connectors = [ class Platform(EfinixPlatform): default_clk_name = "clk33" + default_clk_freq = 33.333e6 default_clk_period = 1e9/33.333e6 def __init__(self, toolchain="efinity"): diff --git a/litex_boards/platforms/jungle_electronics_fireant.py b/litex_boards/platforms/jungle_electronics_fireant.py index 376463f..82660c5 100644 --- a/litex_boards/platforms/jungle_electronics_fireant.py +++ b/litex_boards/platforms/jungle_electronics_fireant.py @@ -49,6 +49,7 @@ _connectors = [ class Platform(EfinixPlatform): default_clk_name = "clk33" + default_clk_freq = 33.33e6 default_clk_period = 1e9/33.33e6 def __init__(self, toolchain="efinity"): diff --git a/litex_boards/targets/efinix_t8f81_dev_kit.py b/litex_boards/targets/efinix_t8f81_dev_kit.py index 528ca3a..9c91107 100755 --- a/litex_boards/targets/efinix_t8f81_dev_kit.py +++ b/litex_boards/targets/efinix_t8f81_dev_kit.py @@ -13,6 +13,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer from litex.gen import * +from litex.gen.genlib.misc import WaitTimer from litex_boards.platforms import efinix_t8f81_dev_kit @@ -28,16 +29,25 @@ class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq): self.rst = Signal() self.cd_sys = ClockDomain() + self.cd_rst = ClockDomain(reset_less=True) # # # clk33 = platform.request("clk33") rst_n = platform.request("user_btn", 0) + self.comb += self.cd_rst.clk.eq(clk33) + + # A pulse is necessary to do a reset. + self.rst_pulse = Signal() + self.reset_timer = reset_timer = ClockDomainsRenamer("rst")(WaitTimer(25e-6*platform.default_clk_freq)) + self.comb += self.rst_pulse.eq(self.rst ^ reset_timer.done) + self.comb += reset_timer.wait.eq(self.rst) + # PLL. self.pll = pll = TRIONPLL(platform) - self.comb += pll.reset.eq(~rst_n | self.rst) - pll.register_clkin(clk33, 33.333e6) + self.comb += pll.reset.eq(~rst_n | self.rst_pulse) + pll.register_clkin(clk33, platform.default_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/efinix_ti375_c529_dev_kit.py b/litex_boards/targets/efinix_ti375_c529_dev_kit.py index 6b0f2b2..ecd7dd6 100755 --- a/litex_boards/targets/efinix_ti375_c529_dev_kit.py +++ b/litex_boards/targets/efinix_ti375_c529_dev_kit.py @@ -10,6 +10,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer from litex.gen import * +from litex.gen.genlib.misc import WaitTimer from litex.build.io import DDROutput, SDROutput, SDRTristate from litex.build.generic_platform import Subsignal, Pins, Misc, IOStandard @@ -39,11 +40,12 @@ from liteeth.phy.trionrgmii import LiteEthPHYRGMII class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq, cpu_clk_freq): - #self.rst = Signal() + self.rst = Signal() self.cd_sys = ClockDomain() self.cd_usb = ClockDomain() self.cd_video = ClockDomain() self.cd_cpu = ClockDomain() + self.cd_rst = ClockDomain(reset_less=True) # # # @@ -51,10 +53,18 @@ class _CRG(LiteXModule): clk100 = platform.request("clk100") rst_n = platform.request("user_btn", 0) + self.comb += self.cd_rst.clk.eq(clk100) + + # A pulse is necessary to do a reset. + self.rst_pulse = Signal() + self.reset_timer = reset_timer = ClockDomainsRenamer("rst")(WaitTimer(25e-6*platform.default_clk_freq)) + self.comb += self.rst_pulse.eq(self.rst ^ reset_timer.done) + self.comb += reset_timer.wait.eq(self.rst) + # PLL. self.pll = pll = TITANIUMPLL(platform) - self.comb += pll.reset.eq(~rst_n) - pll.register_clkin(clk100, 100e6) + self.comb += pll.reset.eq(~rst_n | self.rst_pulse) + pll.register_clkin(clk100, platform.default_clk_freq) # You can use CLKOUT0 only for clocks with a maximum frequency of 4x # (integer) of the reference clock. If all your system clocks do not fall within # this range, you should dedicate one unused clock for CLKOUT0. diff --git a/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py b/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py index 9f3c539..bf03dbb 100755 --- a/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py +++ b/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py @@ -10,6 +10,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer from litex.gen import * +from litex.gen.genlib.misc import WaitTimer from litex_boards.platforms import efinix_titanium_ti60_f225_dev_kit @@ -31,16 +32,25 @@ class _CRG(LiteXModule): self.cd_sys = ClockDomain() self.cd_sys2x = ClockDomain() self.cd_sys2x_ps = ClockDomain() + self.cd_rst = ClockDomain(reset_less=True) # # # clk25 = platform.request("clk25") rst_n = platform.request("user_btn", 0) + self.comb += self.cd_rst.clk.eq(clk25) + + # A pulse is necessary to do a reset. + self.rst_pulse = Signal() + self.reset_timer = reset_timer = ClockDomainsRenamer("rst")(WaitTimer(25e-6*platform.default_clk_freq)) + self.comb += self.rst_pulse.eq(self.rst ^ reset_timer.done) + self.comb += reset_timer.wait.eq(self.rst) + # PLL self.pll = pll = TITANIUMPLL(platform) - self.comb += pll.reset.eq(~rst_n | self.rst) - pll.register_clkin(clk25, 25e6) + self.comb += pll.reset.eq(~rst_n | self.rst_pulse) + pll.register_clkin(clk25, platform.default_clk_freq) # You can use CLKOUT0 only for clocks with a maximum frequency of 4x # (integer) of the reference clock. If all your system clocks do not fall within # this range, you should dedicate one unused clock for CLKOUT0. diff --git a/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py b/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py index 587ec5f..22aee54 100755 --- a/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py +++ b/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py @@ -13,6 +13,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer from litex.gen import * +from litex.gen.genlib.misc import WaitTimer from litex_boards.platforms import efinix_trion_t120_bga576_dev_kit @@ -29,20 +30,27 @@ from liteeth.phy.trionrgmii import LiteEthPHYRGMII class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq): - #self.rst = Signal() + self.rst = Signal() self.cd_sys = ClockDomain() + self.cd_rst = ClockDomain(reset_less=True) # # # clk40 = platform.request("clk40") rst_n = platform.request("user_btn", 0) + self.comb += self.cd_rst.clk.eq(clk40) + + # A pulse is necessary to do a reset. + self.rst_pulse = Signal() + self.reset_timer = reset_timer = ClockDomainsRenamer("rst")(WaitTimer(25e-6*platform.default_clk_freq)) + self.comb += self.rst_pulse.eq(self.rst ^ reset_timer.done) + self.comb += reset_timer.wait.eq(self.rst) # PLL self.pll = pll = TRIONPLL(platform) - #self.comb += pll.reset.eq(~rst_n | self.rst) - self.comb += pll.reset.eq(~rst_n) - pll.register_clkin(clk40, 40e6) + self.comb += pll.reset.eq(~rst_n | self.rst_pulse) + pll.register_clkin(clk40, platform.default_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True, name="axi_clk") # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py b/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py index 04db654..a082961 100755 --- a/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py +++ b/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py @@ -35,6 +35,7 @@ class _CRG(LiteXModule): self.rst = Signal() self.cd_sys = ClockDomain() self.cd_sys_ps = ClockDomain() + self.cd_rst = ClockDomain(reset_less=True) # # # @@ -42,16 +43,18 @@ class _CRG(LiteXModule): clk50 = platform.request("clk50") rst_n = platform.request("user_btn", 0) + self.comb += self.cd_rst.clk.eq(clk50) + # A pulse is necessary to do a reset. self.rst_pulse = Signal() - reset_timer = WaitTimer(25e-6*sys_clk_freq) + self.reset_timer = reset_timer = ClockDomainsRenamer("rst")(WaitTimer(25e-6*platform.default_clk_freq)) self.comb += self.rst_pulse.eq(self.rst ^ reset_timer.done) self.comb += reset_timer.wait.eq(self.rst) # PLL. self.pll = pll = TRIONPLL(platform) self.comb += pll.reset.eq(~rst_n | self.rst_pulse) - pll.register_clkin(clk50, 50e6) + pll.register_clkin(clk50, platform.default_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True) pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180) diff --git a/litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py b/litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py index e117289..92133db 100755 --- a/litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py +++ b/litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py @@ -10,6 +10,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer from litex.gen import * +from litex.gen.genlib.misc import WaitTimer from litex_boards.platforms import efinix_trion_t20_mipi_dev_kit @@ -26,16 +27,25 @@ class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq): self.rst = Signal() self.cd_sys = ClockDomain() + self.cd_rst = ClockDomain(reset_less=True) # # # clk50 = platform.request("clk50") rst_n = platform.request("user_btn", 0) + self.comb += self.cd_rst.clk.eq(clk50) + + # A pulse is necessary to do a reset. + self.rst_pulse = Signal() + self.reset_timer = reset_timer = ClockDomainsRenamer("rst")(WaitTimer(25e-6*platform.default_clk_freq)) + self.comb += self.rst_pulse.eq(self.rst ^ reset_timer.done) + self.comb += reset_timer.wait.eq(self.rst) + # PLL self.pll = pll = TRIONPLL(platform) - self.comb += pll.reset.eq(~rst_n | self.rst) - pll.register_clkin(clk50, 50e6) + self.comb += pll.reset.eq(~rst_n | self.rst_pulse) + pll.register_clkin(clk50, platform.default_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/efinix_xyloni_dev_kit.py b/litex_boards/targets/efinix_xyloni_dev_kit.py index 1dfcc5c..17fbb7f 100755 --- a/litex_boards/targets/efinix_xyloni_dev_kit.py +++ b/litex_boards/targets/efinix_xyloni_dev_kit.py @@ -12,6 +12,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer from litex.gen import * +from litex.gen.genlib.misc import WaitTimer from litex_boards.platforms import efinix_xyloni_dev_kit @@ -27,16 +28,25 @@ class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq): self.rst = Signal() self.cd_sys = ClockDomain() + self.cd_rst = ClockDomain(reset_less=True) # # # clk33 = platform.request("clk33") rst_n = platform.request("user_btn", 0) + self.comb += self.cd_rst.clk.eq(clk33) + + # A pulse is necessary to do a reset. + self.rst_pulse = Signal() + self.reset_timer = reset_timer = ClockDomainsRenamer("rst")(WaitTimer(25e-6*platform.default_clk_freq)) + self.comb += self.rst_pulse.eq(self.rst ^ reset_timer.done) + self.comb += reset_timer.wait.eq(self.rst) + # PLL. self.pll = pll = TRIONPLL(platform) - self.comb += pll.reset.eq(~rst_n | self.rst) - pll.register_clkin(clk33, 33.333e6) + self.comb += pll.reset.eq(~rst_n | self.rst_pulse) + pll.register_clkin(clk33, platform.default_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/jungle_electronics_fireant.py b/litex_boards/targets/jungle_electronics_fireant.py index 91e288c..a6fa79b 100755 --- a/litex_boards/targets/jungle_electronics_fireant.py +++ b/litex_boards/targets/jungle_electronics_fireant.py @@ -13,6 +13,7 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer from litex.gen import * +from litex.gen.genlib.misc import WaitTimer from litex_boards.platforms import jungle_electronics_fireant @@ -31,16 +32,25 @@ class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq): self.rst = Signal() self.cd_sys = ClockDomain() + self.cd_rst = ClockDomain(reset_less=True) # # # clk33 = platform.request("clk33") rst_n = platform.request("user_btn", 0) + self.comb += self.cd_rst.clk.eq(clk33) + + # A pulse is necessary to do a reset. + self.rst_pulse = Signal() + self.reset_timer = reset_timer = ClockDomainsRenamer("rst")(WaitTimer(25e-6*platform.default_clk_freq)) + self.comb += self.rst_pulse.eq(self.rst ^ reset_timer.done) + self.comb += reset_timer.wait.eq(self.rst) + # PLL. self.pll = pll = TRIONPLL(platform) - self.comb += pll.reset.eq(~rst_n | self.rst) - pll.register_clkin(clk33, 33.333e6) + self.comb += pll.reset.eq(~rst_n | self.rst_pulse) + pll.register_clkin(clk33, platform.default_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True) # Default peripherals