diff --git a/litex_boards/targets/1bitsquared_icebreaker.py b/litex_boards/targets/1bitsquared_icebreaker.py
index 18cebf6..4bed916 100755
--- a/litex_boards/targets/1bitsquared_icebreaker.py
+++ b/litex_boards/targets/1bitsquared_icebreaker.py
@@ -95,8 +95,20 @@ class BaseSoC(SoCCore):
         self.submodules.spram = Up5kSPRAM(size=128*kB)
         self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128*kB))
 
+
         # SPI Flash --------------------------------------------------------------------------------
-        self.add_spi_flash(mode="1x", dummy_cycles=8)
+        use_litespi = False
+        if use_litespi:
+            from litespi.modules import W25Q128JV
+            from litespi.opcodes import SpiNorFlashOpCodes as Codes
+            from litespi.phy.generic import LiteSPIPHY
+            from litespi import LiteSPI
+            self.submodules.spiflash_phy  = LiteSPIPHY(platform.request("spiflash4x"), W25Q128JV(Codes.READ_1_1_4))
+            self.submodules.spiflash_mmap = LiteSPI(self.spiflash_phy, clk_freq=sys_clk_freq, mmap_endianness=self.cpu.endianness)
+            spiflash_region = SoCRegion(origin=self.mem_map.get("spiflash", None), size=W25Q128JV.total_size, cached=False)
+            self.bus.add_slave(name="spiflash", slave=self.spiflash_mmap.bus, region=spiflash_region)
+        else:
+            self.add_spi_flash(mode="1x", dummy_cycles=8)
 
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(