From 11405d9ee340cdae33eaaa98469f9e9a43de26dc Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 18 Feb 2021 19:30:05 +0100 Subject: [PATCH] targets/sds1104xe/BaseSoC: Enable Etherbone by default also defaults to Crossover UART when kwargs is empty. --- litex_boards/targets/sds1104xe.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex_boards/targets/sds1104xe.py b/litex_boards/targets/sds1104xe.py index 886a179..375c599 100755 --- a/litex_boards/targets/sds1104xe.py +++ b/litex_boards/targets/sds1104xe.py @@ -61,11 +61,11 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(100e6), with_etherbone=False, eth_ip="192.168.1.50", **kwargs): + def __init__(self, sys_clk_freq=int(100e6), with_etherbone=True, eth_ip="192.168.1.50", **kwargs): platform = sds1104xe.Platform() # SoCCore ---------------------------------------------------------------------------------- - if kwargs["uart_name"] == "serial": + if kwargs.get("uart_name", "serial") == "serial": kwargs["uart_name"] = "crossover" # Defaults to Crossover UART. SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Siglent SDS1104X-E",