From 12b91eccdc44c0516eb48d9b2dc6ec5248d9e2cd Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 14 Feb 2022 10:45:29 +0100 Subject: [PATCH] digilent_arty: Remove yosys+nextpnr INTERNAL_VREF constraint skip (now directly done in LiteX). --- litex_boards/platforms/digilent_arty.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/litex_boards/platforms/digilent_arty.py b/litex_boards/platforms/digilent_arty.py index 2044805..f80e14b 100644 --- a/litex_boards/platforms/digilent_arty.py +++ b/litex_boards/platforms/digilent_arty.py @@ -349,8 +349,7 @@ class Platform(XilinxPlatform): self.toolchain.additional_commands = \ ["write_cfgmem -force -format bin -interface spix4 -size 16 " "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] - if toolchain != "yosys+nextpnr": #this is not supported by yosys+pnr - self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]") + self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]") def create_programmer(self): bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit"